Does anyone know of a web site where I can find a list of 32-bit MIPS instructions/opcodes, with the following features: Clearly distinguishes between real opcodes and assembly-language macros Describes the instruction behavior including differences depending on privilege level. Indicates in which instruction set revision the instructi...
I can understand how one can write a program that uses multiple processes or threads: fork() a new process and use IPC, or create multiple threads and use those sorts of communication mechanisms. I also understand context switching. That is, with only once CPU, the operating system schedules time for each process (and there are tons of ...
What exactly do this instruction? I know that it try to align data with a multiple of a especific number but, why would you need to do this? Is there an equivalent instruccion in other assemblers? ...
The Java Virtual Machine Instruction Set page provides information about mnemonics such as aaload, aastore... etc. However neither the cpu cycles that these mnemonics would take up is mentioned nor is there any info on the byte size or word size of these mnemonics. Any idea where this information could be found? ...
Microsoft offers the InterlockedCompareExchange function for performing atomic compare-and-swap operations. There is also an _InterlockedCompareExchange intrinsic. On x86 these are implemented using the cmpxchg instruction. However, reading through the documentation on these three approaches, they don't seem to agree on the alignment r...
Do graphic cards have instruction sets of their own? I assume they do, but I have been wondering if it is proprietary or if there is some sort of open standard. Is every GPU instruction preceded by a CPU instruction or is it seamless? That is does OpenGL or DirectX call on the driver layer via the CPU which then sends a GPU instruction...
I'm somewhat new to assembly and have to look up the x86 instructions every now and then. Searching the web for every other opcode gets annoying after a while. Then there are the Intel Reference Manuals, but the contents page doesn't have direct links to the various sections in the pdf file, and doesn't list the 'true' page name but inst...
Windows runs on x86 based CPUs only. Is it possible to make Windows run on non-x86 architecture CPUs like POWER, SPARC, ARM, etc.... I know that there is a program viz., Virtual PC 7 for Mac that allows Windows to be run on PowerPC inside MAC OS but not much detail available.... I'm talking about virtualization in a sense that allows HOS...
Does anyone know of any .NET genetic algorithm frameworks for evolving instructions sets in virtual machines to solve abstract problems? I would be particularly interested in a framework which allows virtual machines to self propagate within a pool and evolve against a fitness function determined by a data set with "good" outputs given e...
Hello, Admittedly, I have a bit silly question. Basically, I am wondering if there are some special mechanisms provided by Intel processors to efficiently execute a series of dummy, i.e., NOP instructions? For instance,I could imagine there could be some kind of pre-fetch mechanism that identifies NOPS, discards them and tries to fetch ...
First a little background. The z80 CPU has an instruction called DJNZ which can be used in a similar manner as a for loop. Basically DJNZ decrements the B register and jumps to a label if not zero. For example: ld b,96 ; erase all of the line disp_version_erase_loop: call _vputblank ; eras...
I would like to learn the x86 Instruction Set Architecture. I don't meaning learning an assembly for x86. I want to understand the machine code baby. The reason is that I would like to write an assembler for x86. Then I want to write a compiler that compiles to that assembly. I know that there are the Intel manuals and AMD manuals that...
Every new generation of CPU introduces some sets of new instruction, ie.: MMX,3DNOW,SSE and so on. I've got few general questions about them: 1) If some program uses for example SSE instruction can it be run on CPU that doesn't support SSE? 2) If yes , does it mean that those instuction will be changed to some greater number of simpler ...
0x004012d0 <main+0>: push %ebp 0x004012d1 <main+1>: mov %esp,%ebp 0x004012d3 <main+3>: sub $0x28,%esp If the address is not available,can we calculate it ourselves? I mean we only have this: push %ebp mov %esp,%ebp sub $0x28,%esp ...
LEA EAX, [EAX] I encountered this instruction in a binary compiled with the Microsoft C compiler. It clearly can't change the value of EAX. Then why is it there at all? ...
Question What is the (non-trivial) difference between the following two x86 instructions? 39 /r CMP r/m32,r32 Compare r32 with r/m32 3B /r CMP r32,r/m32 Compare r/m32 with r32 Background I'm building a Java assembler, which will be used by my compiler's intermediate language to produce Windows-32 executables. Currently ...
While building my assembler for the x86 platform I encountered some problems with encoding the JMP instruction: OPCODE INSTRUCTION SIZE EB cb JMP rel8 2 E9 cw JMP rel16 4 (because of 0x66 16-bit prefix) E9 cd JMP rel32 5 ... (from my favourite x86 instruction website, http://siyobik.info/index.php?module=...
Hello, I know about Intel 64 and IA-32 Architectures Software Developer's Manuals. I also know that these cover all the legacy & old processor ISAs. But I want the individual manual (the one that released along with the processor) for each of the processors. I managed to find the 80386 manual EDIT: I'm starting bounty. ...
What are good resources for learning about the x86 instruction set? I'm a total beginner, and have no real understanding of registers, interrupts, address modes etc, so perhaps a generic book on ISAs would be better first. I really have no clue, to be honest. My ultimate goal is to be fluent in x86 assembly. ...
I have the next code: mov ax,@data mov ds,ax Why I can not write just like this? mov ds,@data All source: .MODEL small .STACK 100h .DATA HelloMessage DB 'Hello, world',13,10,'$' .CODE .startup mov ax,@data mov ds,ax mov ah,9 mov dx,OFFSET HelloMessage int 21h mov ah,4ch int 21h E...