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342

answers:

4

Do graphic cards have instruction sets of their own? I assume they do, but I have been wondering if it is proprietary or if there is some sort of open standard.

Is every GPU instruction preceded by a CPU instruction or is it seamless? That is does OpenGL or DirectX call on the driver layer via the CPU which then sends a GPU instruction down the bus or is it more elaborate.

+1  A: 

Yes, the GPU have their own proprietrary instruction sets. The GPU instructions are executed independent from the CPU instructions.

swegi
OK, but how does the OS know to do so? If an OS is compiled for x86, I understand how it knows x86 instructions. But if a system has an ATI card, how does it know to use an ATI instruction set?Does the cpu first call the driver which executes an opengl instruction? What does the routing of instructions to the appropriate resource?
Matt
@Matt: The driver handles all of it; Windows talks to the driver a certain way, and the driver talks to the GPU a certain way.
Jed Smith
+9  A: 

Yes they do. AMD does even provide the specification up to the HD4000 series at the moment.

Take a look here: http://developer.amd.com/gpu_assets/R700-Family_Instruction_Set_Architecture.pdf

There is also a open source project called Nouveau that does reverse engineering of the NV instruction sets.

Note, that NVIDIA has a slightly different architecture than AMD, because they do not use VLIW but scalar execution (although multiple threads are additionally grouped in what is called a Warp or a Wavefront).

Also not every OpenGL/Direct3D call does map to a "GPU instruction". For example when binding a texture the driver will only set appropriate hardware registers that tell the GPU which texture memory to use for sampling.

Real programs are only run when executing shaders or stream processing kernels on the GPU.

Axel Gneiting
A: 

Currently, NVIDIA cards use some kind of intermediate ISA called PTX. You can read about it in this document:

PTX ISA 1.1

PTX programs are translated at install time to the target hardware instruction set.

Locke
A: 

See: CUDA Programming Guide Version 3.0

The compute capability of a device is defined by a major revision number and a minor revision number.

Devices with the same major revision number are of the same core architecture. The major revision number of devices based on the Fermi architecture is 2. Prior devices are all of compute capability 1.x (Their major revision number is 1).

The minor revision number corresponds to an incremental improvement to the core architecture, possibly including new features.

Appendix A lists of all CUDA-enabled devices along with their compute capability. Appendix G gives the technical specifications of each compute capability.

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