JIT-ing on FPGAs ?

Question

Many VMS, JVM/LLVM/... have JITs -- as the code is being interpreted, x86 instructions are created on the fly and executed.

If there something similar to this for FPGAS? Is there someway where as an FPGA is running, I reconfigure it? [If so, please provide project / paper links. If not, what is the technology bottleneck that prevents this from happening?]

Thanks!

Answer 1

The main place this sort of thing is done is in high-end routers and switches. The biggest Cisco and Juniper routers are basically big boards full of FPGAs and PHYs to do the routing, along with a big server to run the routing protocols and compile the tables into the FPGAs. Normally they do this by keeping some portion of the FPGA resources spare to take a new chunk of table processor, and hot-swapping it in once the programming is completed; then the old section can be taken out of service to serve as the next spare.

Answer 2

Is there someway where as an FPGA is running, I reconfigure it?

"partial reconfiguration" may be the phrase to Google for.