views:

98

answers:

2
+3  Q: 

Memory alignment

Hi,

I have understood why memory should be aligned to 4 byte and 8 byte based on data width of the bus. But following statement confuses me

"IoDrive requires that all I/O performed on a device using O_DIRECT must be 512-byte alligned and a multiple of 512 bytes in size."

What is the need for aligning address to 512 bytes.

+4  A: 

Usually large alignment requirements like that are due to underlying DMA hardware. Large block transfers can sometimes be made much faster by requiring much stronger alignment restrictions than what you have here.

On several ARM processors, the first level translation table has to be aligned on a 16 KB boundary!

Carl Norum
@Carl how is it made faster by aligning to 512 bytes as if data is transfered 4 bytes in a cycle
siri
@siri, that's the point - it might not be. It might be transferred 8, 16, 32, or even more, like all 512 bytes in a single cycle. DMA hardware can do basically anything - it's all very implementation dependent.
Carl Norum
@siri: It is made faster by not having the processor involved in the transmission at all (that is what DMA is all about), but DMA hardware sometimes imposes limits above and beyond those implicit in the architecture itself.
dmckee
+1 @dmckee, that's a good explanation.
Carl Norum
A much nicer explanation than mine, and you used the magic word "DMA"
Matt Joiner
A: 

If you don't know what you're doing, don't use O_DIRECT.

O_DIRECT means "direct device access". This means it bypasses all OS caches, hitting the disk (or possibly RAID controller, etc) directly. Disk accesses are on a per-sector basis.

EDIT: The alignment requirement is for the IO offset/size; it's not usually a memory-alignment requirement.

EDIT: If you're looking at this page (it appears to be the only hit), it also says that the memory must be page-aligned.

tc.