With Blackfin processors, I can declare a variable with "l1_data" attribute in gcc, and that variable stays in L1 data SRAM. Is there a way to do this on x86 or x86_64?
+2
A:
No there isn't. It wouldn't really make sense to allow something like that for 3 reasons:
- Considering the size (and associativities) of the L2/L3 caches of modern x86 it's quite likely that a variable where that would make sense would mostly stay in cache anyways.
- Allowing such an option would make the cache structure more complex (since it has to support "pinned" memory.
- It doesn't interact well with threading. What would happen if the thread is changed, which more or less leads to a cacheflush. If the variables stayed in the cache this would allow one program to completely block the cache which wouldn't go to well. Otherwise, what would the point of such an option be?
While I don't know about the Blackfin processor a quick search suggests the L1 isn't completely organized as a cache, but consists of one part cache and one part explicit addressable memory. So in taht case the attribute will most likely create the variable in the explicit addressable potion, which makes much more sense then pinning some variable in a cache. Those processros probably won't have quite as much running threads as a typical fesktop cpu, so that makes sense.
Grizzly
2010-10-09 18:16:56