State to std_logic

Question

Hi all,

I have defined my state as follows:

type state_type is (s0, s1, s2, s3);
signal state   : state_type;

Now I would like to use this state information to form another signal

signal data : std_logic_vector(3 downto 0);
signal data_plus_state : std_logic_vector(5 downto 0);

....
data_plus_state <= data & state;

Does anyone know how I can concert state into a std_logic_vector so that I can concatenate these two signals?

Many thanks, Rob

Answer 1

Define a subprogram that convert state to std_logic_vector.

That subprogram contains a case statement, something like:

case state is
  when s0 => return <std_logic_vector value for s0>;
  when s1 => return <std_logic_vector value for s1>;
  when s2 => return <std_logic_vector value for s2>;
  when s3 => return <std_logic_vector value for s3>;
end case;

Answer 2

Hi Rob

The subprogram and case answer would work very well. If you wanted something in line you could use this.

signal state_slv : std_logic_vector(1 downto 0);

state_slv <= "00" when state = s0 else
             "01" when state = s1 else
             "10" when state = s2 else
             "11";

data_plus_state <= data & state_slv;

Cheers

Answer 3

Hi Rob,

It seems you want to put two (or more) signals into one signal (or port).

The way to go here is not concatenating the signals, but rather put them in a record. The advantage is that the semantics (the meaning) of each part of the signal is clearly expressed. This way you don't have to encode (and later decode) every data element.

type state_type is (s0, s1, s2, s3);
signal state   : state_type;
signal data : std_logic_vector(3 downto 0);
type data_plus_state_type is record
    data : std_logic_vector(3 downto 0);
    state: state_type;
end record data_plus_state_type;
signal data_plus_state : data_plus_state_type;

Then you can put the two signals in a single record signal:

data_plus_state <= (data, state);
-- or:
data_plus_state.data <= data;
data_plus_state.state <= state;