Makefile, source in multiple directories, dependency problem

Answer 1

You really need to add a rule which knows how to make libA and libB, then add the dependency from test onto that rule. The rule can either call make in that directory (recursive make), or explicitly encode the rules for building the libs in your makefile. The first one is more traditional and is pretty simple to understand. It works with almost all situations you will encounter in the field, but there are some potential issues that can arise if you have more complex build setup (I would probably go with it anyway because it is simpler).

Answer 2

make -C dir is your friend here. Do something like:

PROJECTS = A B C D

build:
    for dir in $(PROJECTS); do \
        $(MAKE) -C $$dir build; \
    done

And list your sub-projects in the order you want them to be built.

Answer 3

Try scons ...

Answer 4

I do something like this:

 A/
  Makefile
  A.hpp
  A.cpp
 B/
  Makefile
  B.hpp
  B.cpp
 Makefile
 test.cpp

file A/Makefile:

 LIB = libA.so
 OBJS = A.o

 all: compile link

 compile: ${OBJS}

 link:
  g++ -shared -o ${LIB} ${OBJS}

 clean:
  rm -f ${OBJS}

 A.o:
  g++ -c A.cpp

file B/Makefile:

 LIB = libB.so
 OBJS = B.o

 all: compile link

 compile: ${OBJS}

 link:
  g++ -shared -o ${LIB} ${OBJS}

 clean:
  rm -f ${OBJS}

 B.o:
  g++ -c B.cpp

file Makefile:

DIRS = A B
 OUTPUT = test
 LD = -L. -LA -LB -lA -lB
 OBJS = test.o

 all: compile link

 compile: ${OBJS}
  for DIR in ${DIRS}; do \
   make -C $${DIR} compile; \
  done

 link:
  for DIR in ${DIRS}; do \
   make -C $${DIR} link; \
  done
  g++ -o ${OUTPUT} ${OBJS} ${LD}

 clean:
  for DIR in ${DIRS}; do \
   make -C $${DIR} clean; \
  done
  rm -f ${OBJS}

Then you can:

 make compile
 make link

Or just:

 make

Everything, also in the subdirectories, will be compiled and linked together