Are machine word size (or smaller) writes serialized? Only one native opcode is needed to copy register content to RAM.
A:
Two CPU's may issue the command at the same time, but doesn't the RAM controller have to process each command it receives individually? So, maybe to the CPU's it is simultaneous, but the RAM controller will determine whose command is processed first.
Zachery Delafosse
2009-02-05 17:32:37
+2
A:
There is nothing that prevents you from doing this on a low level. RAM writes are atomic however, so memory controller will execute 2 seemingly simulateneous writes from cores sequentially.
xelurg
2009-02-05 17:33:18
Actually, that only goes for cores on the same CPU, not for separate CPUs, right?
T.E.D.
2009-02-05 17:40:48
AFAIR, it depends on the implementation. Memory contoller is ultimately what decides how to write data to RAM. CPU just issues command to it and provides data via data bus and address via address bus.
xelurg
2009-02-05 17:46:06
A:
They shouldn't because the resulting RAM content would be unspecified if different values were written.
Zach Scrivena
2009-02-05 17:34:34
in fact it will be the value of the latest data register submitted to the write pipeline in memory controller
xelurg
2009-02-05 17:36:30
@xelurg: I agree. But in that case the actual writes are not simultaneous (since they have to be pipelined). In other words, it wouldn't make sense to have two independent write pipelines for the same memory.
Zach Scrivena
2009-02-05 17:46:37
A:
Isn't that native opcode more likely to be writing to the on-CPU cache than directly to RAM?
ChrisW
2009-02-05 17:39:08
Aren't CPU caches write-through? Does it matter in context of atomicity?
Jacek Ławrynowicz
2009-02-05 17:41:33
I think you're referring to the micro-code, which is set of signal levels applied to elements within a CPU...opcode is a higher level - it can operate on various set of elements, including memory and I/O port.http://en.wikipedia.org/wiki/Opcode
xelurg
2009-02-05 17:42:26
forgot to include a link to microcode blurb :) http://en.wikipedia.org/wiki/Microcode
xelurg
2009-02-05 17:47:10
yabcok: I meant ChrisW is referring to microcode when saying that opcode is more likely to write to cache rather then RAM
xelurg
2009-02-05 17:50:15
"Aren't CPU caches write-through?" Googling suggests that writes can be "write-back" instead of "write-through", and that some (Intel) CPUs use a hybrid "write-back" and "write-through". Opcodes aren't as 1-to-1 as they used to be with what's happening at the hardware level.
ChrisW
2009-02-05 17:57:39
A:
They can try, but hardware will be the ultimate determinant of what happens.
MSN
2009-02-05 17:59:32
It's still up to the hardware, and by hardware I mean how the CPU interfaces with memory.
MSN
2009-02-05 19:44:00
+3
A:
Writing data to RAM is atomic. If two CPUs try to write to the same location at the same time, the memory controller will decide on some order for the writes. While one CPU is writing to memory, the other CPU will stall for as many cycles as necessary until the first write is completed; then it will overwrite its value. This is what's known as a race condition.
Writes that are smaller than the native word size are not atomic -- in that case, the CPU must read the old memory value into a register, write the new bytes into the register, and then write that new value back to memory.
You should never have code that depends on this -- if you have multiple CPUs that are trying to simultaneously write to the same memory location, you're doing something wrong.
Another important consideration is the cache coherency problem. Each CPU has its own cache. If a CPU writes data to its cache, the other CPUs need to be made aware of the change to that data value if they want to read it.
Adam Rosenfield
2009-02-05 18:07:12