makefile

Variations of sed between OSX and GNU/Linux

Hi all- I've got a makefile (developed for gmake on Linux) that I'm attempting to port to OSX, but it seems like sed doesn't want to cooperate. What I do is use GCC to autogenerate dependency files, and then tweak them a bit using sed. The relevant portion of the makefile: $(OBJ_DIR)/%.d: $(SRC_DIR)/%.cpp $(CPPC) -MM -MD $< -o $@ ...

Makefile include .depend

In my makefile, I have a: include .depend I also have a depend: rules for buiding .depend Now, here is the problem, when ".depend" does not exist, I can't run "make depend"; I have to do "touch .depend; make depend" Is there anyway to tell Make "if .depend does not exist, still allow me to run 'make depend'" ? Thanks! ...

Problem with makefile

Hello. I created a python project in IDE Anjuta, added some python files and the problem follows. I need that would make the program after a few .py files lying in src copied to dir /usr/bin. Anjuta generates enormous configure- and makefiles. 'll Show you need to register and where that would make described above. Thank you. ...

Makefile problem with files beginning with "#"

I have a directory "FS2" that contains the following files: #ARGH# this that I have a makefile with the following contents. Template:sh= ls ./FS2/* #all: $(Template) echo "Template is: $(Template)" touch all When I run "clearmake -C sun" and the file "all" does not exist, I get the following output: "Template is: ...

What's a good directory structure for larger C++ projects using Makefile ?

What's a good directory structure for larger C++ projects using Makefile ? This is how my directory structure looks at the moment: lib/ (class implementations *.cpp) include/ (class definitions *.h) tests/ (main.cpp for quick tests) Now, I'm not sure how my Makefile should look like... it doesn't seem to work when .cpp files and .h f...

How does the make "-j" option actually work ?

From the man pages: -j [jobs], --jobs[=jobs] Specifies the number of jobs (commands) to run simultaneously. If there is more than one -j option, the last one is effective. If the -j option is given without an argument, make will not limit the number of jobs that can run simultaneously. I know i...

Creating a Cross-Platform C++ Library

Hello people, I wanted to create a cross-platform 2D game engine, and I would like to know how to create a cross-platform project with Makefile, so I can compile it to the platforms I choose with custom rule for any platform. I'm working on the windows enviroment with Visual C++ Express 2008, so it would be nice if I can use Visual C++ E...

Assign a makefile variable value to a bash command result ?

Hello , I'm trying to assign the output of this command ( that is in my makefile ) to the makefile HEADER var like in this following line of code: HEADER = $(shell for file in `find . -name *.h`;do echo $file; done) The problem is that if I print HEADER in my makefile using: print: @echo $(HEADER) I get ile ile ile ile ile il...

Makefile Build Directory and dependencies list

Hello, In a makefile, I build all my .o files in a build directory: program: class1.o class2.o class3.o g++ $(BUILDDIR)class1.o $(BUILDDIR)class2.o $(BUILDDIR)class3.o -o $@ It would be cool to generate $(BUILDDIR)class1.o $(BUILDDIR)class2.o $(BUILDDIR)class3.o from the dependencies list... I know that $^ would give me the list...

Creating a directed acyclic graph out of recursive nmake makefile?

Hello, As an exercise and in an effort to (better understand|help other people better understand) the build process at my company, I am hoping to create a directed acyclic graph of the build process. The current build process at my work is, as I understand, is essentially running nmake on a makefil at the root build directory. This m...

my makefile's target-specific variable doesn't affect recursively expanded variables

In my makefile (rather simplified below) I have a target-specific variable that needs to influence a recursively expanded variable, but it's not doing so - leaving me sitting here scratching my head: NAME = MyProg OBJECTS = $(OD)/main.o RD = Release OD = Foo all: OD = $(RD) all: $(OD) $(OD)/...

Escaping in makefile

I'm trying to do this in a makefile and it fails horribly: M_ARCH := $(shell g++ -dumpmachine | awk '{split($1,a,"-");print a[1]}') do you know why? I guess it has to do with escaping, but what and where? ...

Are there any good tools for examining Makefiles?

Large complex make files can be daunting to read and examine. What tools are good for visualizing or otherwise examining a gnu make file? ...

PHP error: libphp5.so: undefined symbol: _estrndup

I compile Apache-MySQL-PHP by hand to build a custom install using the configure options from below. When I start apache it fails to start and adds the below error in the error_log. * Apache 2 * Mysql 5.0 * PHP 5.1 * CentOS Linux 5.4 * GCC compiler the error in apache log httpd: Syntax error on line 54 of /opt/clamp/etc/httpd.conf: Can...

Make, inherit rules in subdirectory Makefile

I want to set up a system of Makefiles in my project directories so that the rules defined in one will be defined in others. Let's say for example I have a directory called "test" and inside is "test.c" but I want to build test.c using a rule defined in a Makefile in the root directory Here is an example #Makefile (inside base dir) %....

Makefile, header dependencies

Let's say I have a makefile with the rule %.o: %.c gcc -Wall -Iinclude ... I want *.o to be rebuilt whenever a header file changes. Rather than work out a list of dependencies, whenever any header file in /include changes, then all objects in the dir must be rebuilt. I can't think of a nice way to change the rule to accomodate this...

Makefiles: how to get a file name for a rule target from outside, in a portable way

I need to get some external data to form an output file name in a Makefile. In GNU Make I can do something like this : NAME=$(shell some_commands) $(NAME).out: file.in compile "$<" -o "$@" Some other rules have $(NAME).out as a prerequisite so I need $(NAME).out as a target. I can't use substitution+quotes here as this is not in...

Log invoked commands of make

Is there a way to log the commands, make invokes to compile a program? I know of the parameters -n and -p, but they either don't resolve if-conditions but just print them out. Or they don't work, when there are calls to 'make' itself in the Makefile. ...

GNU Make: How to call $(wildcard) within $(eval)

I'm trying to create a generic build template for my Makefiles, kind of like they discuss in the eval documentation. I can't seem to get the wildcard function to work within an eval. The basic code I'm having issues with looks like this. SRC_DIR = ./src/ PROG_NAME = test define PROGRAM_template $(1)_SRC_DIR = $(join $(SRC_DIR), $(...

Building multiple binaries within one Eclipse project

How can I get Eclipse to build many binaries at a time within one project (without writing a Makefile by hand)? I have a CGI project that results in multiple .cgi programs to be run by the web server, plus several libraries used by them. The hand-made Makefile used to build it slowly becomes unmaintainable. We use Eclipse's "Internal Bu...