Our make file compiles .c source files with a static pattern rule like this: OBJECTS = foo.o bar.o baz.o $(OBJECTS): %.o: %.c $(CC) $< $(C_OPTIONS) -c -o $@ I need to change one of the .c files to an Objective-C .m file. Invoking the compiler is the same for both source types, so I'd like to use the same rule and just tweak it to...
How can I compact the folllowing Makefile targets? $(GRAPHDIR)/Complex.png: $(GRAPHDIR)/Complex.dot dot $(GRAPHDIR)/Complex.dot -Tpng -o $(GRAPHDIR)/Complex.png $(GRAPHDIR)/Simple.png: $(GRAPHDIR)/Simple.dot dot $(GRAPHDIR)/Simple.dot -Tpng -o $(GRAPHDIR)/Simple.png $(GRAPHDIR)/IFileReader.png: $(GRAPHDIR)/IFileReader....
Here is the scoop: command I am Invoking: make -d I get this error: Finished prerequisites of target file `stopwatch.obj'. Must remake target `stopwatch.obj'. Creating temporary batch file C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp\make35562.sh cl /I .\include /I "c:\Java\jdk150_13\include\win32" /I "c:\Java\jdk150_13\include" /Fo".\buil...
I'm trying to debug a complex Makefile. How do you get GNU make to print all the commands it runs? I couldn't find the answer in the man page (using the -d flag doesn't seem to print it). (This isn't necessary info to answer my question, but in case you're wondering: I'm having trouble compiling a project built on NVIDIA's CUDA library...
In my GNUmakefile, I would like to have a rule that uses a temporary directory. For example: out.tar: TMP := $(shell mktemp -d) echo hi $(TMP)/hi.txt tar -C $(TMP) cf $@ . rm -rf $(TMP) As written, the above rule creates the temporary directory at the time that the rule is parsed. This means that, even I don'...
I have a makefile that depending on some properties sets vpath and generates a list of source files into one variable. I need to run the makefile without compiling anything (the compilation is actually handled by a different makefile) and just see to which real files the filenames get matched depending on the vpath settings. ...
Is there a way to get GNU make to work correctly with filenames that contain colons? The specific problem I'm running into happens to involve a pattern rule. Here's a simplified version that does not depend on cutting and pasting tab characters: % make --version GNU Make 3.81 Copyright (C) 2006 Free Software Foundation, Inc. This is ...
My first question (yay!) is about gnumake and parallel builds. Here's a quick example file: .PHONY: tool_1 tool_2 tool_3 tool_4 all tools all: | tools tools: | tool_2 tool_3 tool_4 tool_1: # commands for tool 1 tool_2: | tool_1 # commands for tool 2 tool_3: | tool_1 # commands for tool 3 tool_4: | tool_1 # command...
I am using a GNU-make Makefile to build a C project with several targets (all, clean, and a few project specific targets). In the process of debugging, I would like to append some flags to a single build without permanently editing the Makefile (e.g. add debugging symbols or set a preprocessor flag). In the past, I have done that as fol...
I have a set of makefiles I use to build a 'big' C project. I am now trying to reuse some in my C++ project and have run into this headache that I just cannot figure out. The makefile looks like this SOURCES = \ elements/blue.cpp # Dont edit anything below here VPATH = $(addprefix $(SOURCE_DIR)/, $(dir $(SOURCES))) CXXFLAGS = $(OPT...
I have a GNU Makefile that looks a bit like this: LIST = item1 .PHONY: targetMain targetA targetB preA preB targetMain: # DO all the work in here echo $(LIST) targetA: preA targetMain targetB: preB targetMain preA: LIST += itemA preB: LIST += itemB The idea is that I either run make targetA or make targetB. Both of them do a ...
After years of not using make, I find myself needing it again, the gnu version now. I'm pretty sure I should be able to do what I want here, but haven't figured out how, or found an answer with Google, etc. I'm trying to create a test target which will execute my program a number of times, saving the results in a log file. Some tests ...
Hi there, I have a Makefile.am which will be responsible for building a final application binary: project/src/Makefile.am also in the src directory is a sub-directory called ctrnn which contains a further Makefile.am: project/src/ctrnn/Makefile.am Now, ctrnn/Makefile.am should only generate object .o files with the idea being that t...
I'm trying to do this in a makefile and it fails horribly: M_ARCH := $(shell g++ -dumpmachine | awk '{split($1,a,"-");print a[1]}') do you know why? I guess it has to do with escaping, but what and where? ...
I'm new to the NDK. (using Windows) I have downloaded cygwin and the NDK. I have unzipped the NDK in C:\ When I run cygwin I change to the NDK directory and I run the command build/host-setup.sh But I get Error: could not find a valid GNU Make executable. I have downloaded GNU make 3.81 but still no luck, What do I have to do with ...
I'm trying to create a generic build template for my Makefiles, kind of like they discuss in the eval documentation. I can't seem to get the wildcard function to work within an eval. The basic code I'm having issues with looks like this. SRC_DIR = ./src/ PROG_NAME = test define PROGRAM_template $(1)_SRC_DIR = $(join $(SRC_DIR), $(...
I'm trying to create a generic build template for my Makefiles, kind of like they discuss in the eval documentation. I've run into a known bug with GNU Make 3.80. When $(eval) evaluates a line that is over 193 characters, Make crashes with a "Virtual Memory Exhausted" error. The code I have that causes the issue looks like this. SRC_...
Hi, I'm playing around with make files and the VPATH variable. Basically, I'm grabbing source files from a few different places (specified by the VPATH), and compile them into the current directory using simply a list of .o-files that I want. So far so good, now I'm generating dependency information into a file called '.depend' and inc...
Hi, I've been a visual studio developer for long and just trying to understand how things are in linux/unix worl. I found an open source project (Gcomandos) in source forge and tried to build it. when I download the source, I get these files: 16/02/2007 05:16 PM 25,987 aclocal.m4 16/02/2007 05:17 PM 127,445 config...
I have a setup where make is going through a bunch of subdirectories and making inside those directories. I would like it to stop the build on a failure immediately. The code snippet below illustrates this. Can someone point me in the right direction on how the makefile should be set up or some documentation about building from a top ...