I am trying to install Steel Bank Common Lisp as described in this article. However, when I do this step: sh-3.2# INSTALL_ROOT=/usr/local sh install.sh I get this error: GNU Make not found. Try setting the environment variable GNUMAKE. How, exactly, do I install GNU Make and set the environment variable GNUMAKE on Mac OS X? ...
Dear gurus, Please consider the following Makefile: CC = g++ CFLAGS = -c -O -Wall EFLAGS = -O -Wall -lm -o UTILITIES = error.o stream_manip.o mat_ops.o GaussElim.o UTILITIES += abstractmatrix.o dvector.o dmatrix.o ConjGrad.o # All objects %.o: %.cpp %.hpp $(CC) $(CFLAGS) $< # Executables (doesn't have extension) % : %.cpp $(...
Given the line: program_OBJS := ${program_SRCS:.cpp=.o} I would like to append .o to each filename instead of replacing .cpp with .o. How do I do that? ...
Lets say I have files: Libs: one.cpp, one.h two.cpp, two.h three.cpp, three.h Program: program.cpp Is there way, to create Makefile which will compile only that *.cpp which were modified from last compilation? Currently I have something like that: SRCS = one.cpp two.cpp three.cpp OBJS = $(SRCS:.cpp=.o) all: $(OBJS) program ....
I would like to perform expansion on a variable that might contain references to other variables. I'll illustrate with an example: a = 1 b = 2 c = 3 X = foo bar baz $(foreach x, a b c, $$(value $(x))) qux $(info $(X)) If you run this makefile, it prints: foo bar baz $(value a) $(value b) $(value c) qux I'd like to know how to expand ...
I have a directory images/ that I want to copy to build/images/ from within a Makefile. The directory might contain multiple levels of subdirectories. What would be the most elegant way to do that? I want: avoid a full directory copy on each make run (i.e. no cp -r) guaranteed consistency (i.e. if a file changed in images/ it should be...
I have a makefile: #Nice, wonderful makefile written by Jason CC=g++ CFLAGS=-c -Wall BASE_DIR:=. SOURCE_DIR:=$(BASE_DIR)/source BUILD_DIR:=$(BASE_DIR)/build TEST_DIR:=$(BASE_DIR)/build/tests MAKEFILE_DIR:=$(BASE_DIR)/makefiles DATA_DIR:=$(BASE_DIR)/data DATA_DIR_TESTS:=$(DATA_DIR)/tests MOLECULE_UT_SOURCES := $(SOURCE_DIR)/molecule_tes...
This is a bit complex so I have uploaded an example here. How to test it: Download the tarball and unpack it cd make_problem/make make aclean (forgot to remove the archive from the archive ;)) make alib (will re-create the simple and silly archive you just removed) ./weird.sh What weird.sh does is simply to touch a source file, re-m...
How to get the invoking target of the gnu makefile? for example, I invoke the makefile with the following command line: make a-target How can I get the invoking target "a-target" in the makefile to assign it to a variable? further more, if more than one target is specified in cmd line: make target1 target2 ... How to get all of the...
I have the following block of code in a makefile: param_test_dir: @if test -d $(BUILD_DIR); then \ echo Build exists...; \ else \ echo Build directory does not exist, making build dir...; \ mkdir $(BUILD_DIR); \ fi @if test -d $(TEST_DIR); then \ echo Tests exists...; \ else \ echo Tests directory does not e...
From the GNU Make manual: The value of the make variable SHELL is not exported. Instead, the value of the SHELL variable from the invoking environment is passed to the sub-make. You can force make to export its value for SHELL by using the export directive, described below. I must be doing something wrong, or not readin...
I have a makefile that takes options at the command line make OPTION_1=1 Based on the value it will add additional compiler definitions to a subset of objects. ifeq ($(OPTION_1), 1) CC_FLAGS += -DOPTION_1_ON endif The change in the definition affects the included header file content - a stub or an implementation is exposed to the ...
hi, codeSourcery G++ Lite Edition is a freeware or Sharware? any help please? please see the link "http://www.codesourcery.com/sgpp/lite_edition.html" ...
In many script files, _DIR_ means the directory where the script file itself is located. Is there any equivalence in GNU Make? ...
Consider, if you will, the following situation: $ pwd /tmp/submake_example $ head $(find -type f) ==> ./subdir/Makefile <== subtarget: echo "executing subtarget from directory $$(pwd)" ==> ./Makefile <== include subdir/Makefile $ make subtarget echo "executing subtarget from directory $(pwd)" executing subtarget from directory ...
This question is similar in spirit to question 2543127. I have a gnu makefile with a list of header files. Each header file may be located in a different directory, e.g., HEADERS = $(wildcard *.h) $(wildcard foo/*.h) $(wildcard bar/*.h) and I want to have the makefile copy all headers to an include directory INCDIR = ../include a...
I'm running a recursive make on windows using targets for each directory using forward slashes to separate path components. If someone runs > make foo/bar it will run fine. But if someone runs > make foo\bar it won't find the target to build: make: Nothing to be done for `foo\bar'. I would love it if I could add something like t...
I have a project whose makefile uses features exclusive to GNU Make. Sadly, there are platforms we must support where GNU make is still not the default when running make. One of my colleagues was bitten by this, when a non-GNU make implementation silently failed to build our code correctly (it expanded an automatic variable to an empty ...
In Make this flag exists: -l [load], --load-average[=load] Specifies that no new jobs (commands) should be started if there are others jobs running and the load average is at least load (a floating-point number). With no argument, removes a previous load limit. Do you have a good strategy for what value to use for the load li...
In the GNU Makefile manual, it mentions these prefixes. If .ONESHELL is provided, then only the first line of the recipe will be checked for the special prefix characters (‘@’, ‘-’, and ‘+’). What do these prefixes do, and where are they mentioned? ...