makefile

Directory as a dependency in make rule

Is it possible to specify a directory as a dependency in a Makefile rule? Actually I have a Makefile in a directory and another directory containing all the source files. . . |_ Makefile |_ src |_a.c |_a.h Now I want that whenever I make any change in the src directory i.e. in either of a.c or a.h , a particular rule in my Mak...

get process id in Makefile

How can I get the pid of my make command in the Makefile? Specifically, I want to use a temp directory that will be unique to this build. I tried: TEMPDIR = /tmp/myprog.$$$$ but this seems to store TEMPDIR as "/tmp/myprog.$$" and then eval as a new pid for every command which refs this! How do I get one pid for all of them (I'd prefe...

ignoring at (@) symbol in makefiles

In makefiles, a line prefixed with an at symbols disables the print of the output. I have a makefile where every line is prefixed with an at, but for debug I need to see what's going on. Is there a way to tell make to ignore the at and output the line ? the debug is excessive, and the -n option prints them, but does not do anything (it's...

MySQL C++ Connector: undefined reference to `get_driver_instance'

Hey, I've been trying to get the MySQL connector working I've installed both the connector and the mysql client library but I am still getting this error: obj/Database.obj: In function `Database::connect()': /home/xeross/alpine/src/server/Database.cpp:13: undefined reference to `get_driver_instance' collect2: ld returned 1 exit status ...

Help with Makefile: No rule to make target

CC = g++ CFLAGS = -Wall RM = /bin/rm -rf BIN_DIR = ifeq "$(DEBUG)" "1" BIN_DIR = Debug else BIN_DIR = Release endif OBJS = \ $(BIN_DIR)/Unit.o $(BIN_DIR)/%.o: src/%.c @echo Building "$@" @g++ -c "$<" -o"$@" all: $(OBJS) clean: $(RM) $(BIN_DIR) .PHONY: all clean However, when I try to build my project this, it gives m...

Create rule in makefile for just a set of files

I am writing a Makefile, and I want to use a generic rule with wildcards, like %: bkp/% cp $< $@ But I wanted this rule to be valid only for a few specific files. I wanted to define a variable with the list, for example file_list = foo.c bar.c zzz.c and configure the rule so it is only valid for files that are listed in this var...

Templated function being reported as "undefined reference" during compilation

These are my files: --------[ c.hpp ]-------- #ifndef _C #define _C #include<iostream> class C { public: template<class CARTYPE> void call(CARTYPE& c); }; #endif --------[ c.cpp ]-------- #include "c.hpp" template<class CARTYPE> void C::call(CARTYPE& c) { //make use of c somewhere here std::cout<<"Car"<<std::endl; } ...

I want to create a makefile *.c to *.o *.o to executable

I want to create a makefile 1) *.c to *.o 2) *.o to executable Thanks in advance ...

Forcing erl -make to recompile files when macros are changed

I tried to do something similar to http://stackoverflow.com/questions/1894363/how-to-make-two-different-source-directories-in-a-makefile-output-to-one-bin-dire/1895096#1895096, so I have these files (relative to my project root): Emakefile: % EMakefile % -*- mode: erlang -*- {["src/*", "src/*/*", "src/*/*/*"], [{i, "include"}, {outdir,...

make to compare two folders

Dear Friends: I want to use a makefile to compare two folders. If the two folders are equal I don't do anything, but if they are different I want to create a folder. Here is my makefile which is complaining about: BINDIREXISTS:=T ifeq "../.build" "../TopicA" /bin/sh: ifeq: not found make: * [checkDest] Error 127 The makefile is the f...

Expression that either returns the output string from a program, or a specific string, if the program doesn't exist

I'm using mercurial as a SCM, and an output from the hg parents command in my makefile to store build number and version information in my program. However, mercurial is not always present on machines where I try to build the program. Thus, hg parent fails. I'd like to use a substitute string (hard-coded or output from other program) whe...

Alternative uses for makefiles

A makefile is typically used for source compilation; however, as a dependency mechanism, make can have many more uses. For a minor example, I have a script that runs daily, and it might update or create some '*.csv.gz' files in a directory based on some web-scraping; all the gzipped files need to be consolidated into one file, and if th...

Makefile conditional include

I'm trying to write an application that needs either ALSA or OSS headers. Basically, I want to pass a define to the compiler if /etc/oss.conf does not exist, since that probably means the soundcard.h header doesn't exist (feel free to correct me on that one, I'm still new to working with OSS). Per the OSS documentation, you would use the...

How do you perform an action over each file using make?

Let's say I have this: FILES = c:/file.c c:/another_file.c and I want to do something to each of the files. For example, I'd like to apply cygpath to each of the files. How can I do that? I would like a solution based on an external program, instead of a built-in make function please. ...

make file issue : always spits out "Nothing to be done for `make.w'."

I have 3 files Head.cpp , Head.h and Hello.cpp . I am trying to build a make for the compilation process. My makefile is make.w Hello : Head.o Hello.o g++ -o Head.o Hello.o Head.o : Head.cpp g++ -o Head.cpp Hello.o: Hello.cpp g++ -o Hello.cpp every time I type the command make make.w - I get " Nothi...

Why does make think the target is up to date?

This is my Makefile: REBAR=./rebar REBAR_COMPILE=$(REBAR) get-deps compile all: compile compile: $(REBAR_COMPILE) test: $(REBAR_COMPILE) skip_deps=true eunit clean: -rm -rf deps ebin priv doc/* docs: $(REBAR_COMPILE) doc ifeq ($(wildcard dialyzer/sqlite3.plt),) static: $(REBAR_COMPILE) build_plt analyze else st...

How can I edit makefile to change Doxyfile settings?

I have the below code in my makefile. The makefile generates a Doxyfile with standard configurations. I want to change the UML_LOOK tag to YES and GENERATE_TREEVIEW to YES without having to edit the file manually. Is there a way of passing commands to the makefile so it does the job itself? doc: doxygen -g Doxyfile doxygen Doxyf...

makefile aliases

Please explain $@ $^ $ in the makefile below LIBS = -lkernel32 -luser32 -lgdi32 -lopengl32 CFLAGS = -Wall # (This should be the actual list of C files) SRC=$(wildcard '*.c') test: $(SRC) gcc -o $@ $^ $(CFLAGS) $(LIBS) ...

makefile aliases

Possible Duplicate: makefile aliases Please explain $@ $^ in the makefile below LIBS = -lkernel32 -luser32 -lgdi32 -lopengl32 CFLAGS = -Wall # (This should be the actual list of C files) SRC=$(wildcard '*.c') test: $(SRC) gcc -o $@ $^ $(CFLAGS) $(LIBS) ...

Compilation error in Makefile, includes not showing up

I have a makefile as follows: CC = gcc CFLAGS = -fmessage-length=0 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" $(INCLUDES) ifdef DEBUG CFLAGS += -g3 endif INCLUDES = \ -I../config.include \ -I../log.include \ -I../services.include SRC_DIR = src BIN_DIR = bin BINARY = report SRCS = $(shell ls $(SRC_DIR)/*.cpp) OBJS = $(SRCS:%.cpp=%....