Makefile rule without dependency expression

Question

Hi folks!

I read the german article about "Make" on Wikipedia and found the following 2 lines:

.c.o:
     $(CC) $(CFLAGS) -c -o $@ $<

Why is the dependency expression left out and why does the target use a double file extension?

Answer 1

That is what is called a 'Suffix Rule', and is used to make a target with the second suffix from a source with the first suffix, as long as the suffixes are known to make. See Suffix Rules in the make manual for a more detailed description

Answer 2

This is actually defining a suffix rule... it is defining how to build a file ending in ".o" from a corresponding file ending in ".c", which tells make to infer that "filename.c", if it exists, is a dependency for "filename.o" for any such filename, and that the "filename.o" file may be built from its *.c dependency with the provided rule.

I should point out, though, that this line is completely unnecessary and is, in fact, not something one should put in a Makefile, since Make is already capable of deducing that type of dependency. You may be interested in my Makefile tutorial as it goes on in quite some detail all the things Make is capable of inferring.