views:

152

answers:

2

Is there a way to reassign Makefile variable value inside of the target body?

What I am trying to do is to add some extra flags for debug compilation:

%.erl: %.beam
    $(ERLC) $(ERLFLAGS) -o ebin $<

test: clean debug_compile_flag compile compile_test

debug_compile:
    $(ERLCFLAGS) += -DTEST

So if I invoke test target I would like to clean up my environment, add some new flags (like -DTEST to the existing ones), compile the whole code once again (first sources, then test modules).

I do not want to copy/paste the code for compiling with some new flags set since there is a lot of logic put here and there.

Is there some easy way to redefine the variable value so I can reuse the existing code?

A: 

No. There is no way to do this in the Makefile. You can however change the value of a variable on the make command line. If you rewrite your Makefile as follows:

ERLCFLAGS += $(ERLCFLAGSADDED)

%.erl: %.beam
    $(ERLC) $(ERLCFLAGS) -o ebin $<

test: clean compile compile_test

Then, you can invoke make to perform your tests using:

make ERLCFLAGSADDED=-DTEST test
Didier Trosset
Yeah, I solved the problem as you suggested, running submake in the debug_compile: ERLC_FLAGS=$(ERLC_DEBUG_FLAGS) $(MAKE) compileThanks!
paulgray
Oh yes, great. I didn't thought about this submake invocation.
Didier Trosset
A: 

Yes, there is an easy way to do it, and without rerunning Make. Use a target-specific variable value:

test: clean debug_compile

debug_compile: $(ERLCFLAGS) += -DTEST
debug_compile: compile compile_test;
Beta