I'm messing around with using Sugiyama's directed graph layout algorithm to generate nice plots of verilog circuits. The problem I'm having is that the layout algorithm assumes that each block (or vertex) has only one input or output edge. But real circuits can have blocks that have multiple input and output connections, which ideally remain in a fixed order.
I was thinking of adding extra vertexes for each input, but somehow treating all the vertices connected to one block as a unit - in Python, something like [ [a.in], [b.in], [c.in1, c.in2] ] where c is a block with 2 inputs. The list would be flattened when building the connection matrices between layers.
Am I on the right track? Is there an easier way to do this? Can you point me to any resources which will help me extend Sugiyama's algorithm to deal with such blocks?