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views:

207

answers:

2

Hi,

I want to do pattern matching rule for camelcase in my makefile:

e.g. Explicit rule:

MyFileName.java: my_file_name.proto protoc --java_out=. $<

I need Pattern matching rule for the above so that just one rule does the job of creating java target of camelcase form from corresponding proto file.

Thnx in advance !!

+2  A: 

Note: I'm assuming you're using Gnu make.

You can't do that directly in Make. The solution is to generate a file containing the rules with a script (using sed or awk, for example). Then include the file in your Makefile. You can define your dependencies so that make regenerates the include file before including it if it is out of date. The Make info pages have more details.

Not all versions of Make have this feature.

Nat
A: 

Never say never !

FILES:=foof_goog.proto zozo_bobo.proto


define makeCamel
$(strip \
$(subst .proto,.java,   \
$(patsubst a%,A%,   \
  $(patsubst b%,B%, \
  $(patsubst c%,C%, \
  $(patsubst d%,D%, \
  $(patsubst e%,E%, \
  $(patsubst f%,F%, \
  $(patsubst g%,G%, \
  $(patsubst h%,H%, \
  $(patsubst i%,I%, \
  $(patsubst j%,J%, \
  $(patsubst k%,K%, \
  $(patsubst l%,L%, \
  $(patsubst m%,M%, \
  $(patsubst n%,N%, \
  $(patsubst o%,O%, \
  $(patsubst p%,P%, \
  $(patsubst q%,Q%, \
  $(patsubst r%,R%, \
  $(patsubst s%,S%, \
  $(patsubst t%,T%, \
  $(patsubst u%,U%, \
  $(patsubst v%,V%, \
  $(patsubst w%,W%, \
  $(patsubst x%,X%, \
  $(patsubst y%,Y%, \
  $(patsubst z%,Z%, \
   $(subst _a,A,    \
   $(subst _b,B,    \
   $(subst _c,C,    \
   $(subst _d,D,    \
   $(subst _e,E,    \
   $(subst _f,F,    \
   $(subst _g,G,    \
   $(subst _h,H,    \
   $(subst _i,I,    \
   $(subst _j,J,    \
   $(subst _k,K,    \
   $(subst _l,L,    \
   $(subst _m,M,    \
   $(subst _n,N,    \
   $(subst _o,O,    \
   $(subst _p,P,    \
   $(subst _q,Q,    \
   $(subst _r,R,    \
   $(subst _s,S,    \
   $(subst _t,T,    \
   $(subst _u,U,    \
   $(subst _v,V,    \
   $(subst _w,W,    \
   $(subst _x,X,    \
   $(subst _y,Y,    \
   $(subst _z,Z,$(1)))))))))))))))))))))))))))))))))))))))))))))))))))))))
endef



all:    $(call makeCamel,$(FILES))



define makeTarget
 $(2):: $(1)
    protoc --java_out=$(2) $(1)

endef
$(foreach x,$(FILES),$(eval $(call makeTarget,$x,$(call makeCamel,$x))))
an0nym0usc0ward
This is not working for me. All I am getting is following:make: Nothing to be done for `all'.
he makefile is just a sample. You need to replace the first line FILES:=xxxx with the list of your .proto files. You will get the message Nothing to be done if either - FILES is empty -or- The corresponding .java files already exist btw: this is for Gnu make
an0nym0usc0ward