GNU make scope of variable
I have some makefile: $(PROGRAM_NAME): index.o @echo "linking" @echo $(index_o) //linking export index_o:=. index.o: $(MAKE) -C some_dir index.o at some_dir makefile export index_o:=$(index_o)/index.o index.o: @echo "compiling" @echo $(index_o) //compiling output: compiling ./index.o linking . need ou...