makefile

Difference between CPPFLAGS and CXXFLAGS in GNU Make

What's the difference between CPPFLAGS and CXXFLAGS in GNU Make? ...

Calling a C++ function from a C program

Hello, How can I call a C++ function from a C program, is it possible?, and if it is how can I do it?. Thank you. ...

Functions in Makefile

Hello! I am writing a Makefile with a lot of repetitive stuff, e.g. debug_ifort_Linux: if [ $(UNAME) = Linux ]; then \ $(MAKE) FC=ifort FFLAGS=$(difort) PETSC_FFLAGS="..." \ TARGET=$@ LEXT="ifort_$(UNAME)" -e syst; \ else ...

Create a file from a large Makefile variable

I have a list of objects in a Makefile variable called OBJECTS which is too big for the command buffer. Therefore I'm using the following method to create a file listing the objects (to pass to ar): objects.lst: $(foreach OBJ,$(OBJECTS),$(shell echo "$(OBJ)">>$@)) While this works it is extremely slow (on Cygwin at least) and I do...

Bash completion for make with generic targets in a Makefile

Hello, I have a Makefile where most of my targets are created generically through a canned sequence. It seems that bash completion only suggests completions for normal targets, e.g. target_name: #$@ and not for generic targets. Is there any way to make bash completion complete all the targets, even though they are not made ex...

What is the difference between -I and -L in makefile?

Where can I find the usage of these stuff? Is there some books that cover them? ...

writing make files

Hi Can anyone point me to some good tutorials on the make utility. Something that will take me through beginners to advanced and let me write and understand professional make file which come with various linux packages. some book also might help. I googled for this , but there are so many. I dont know which one to read. Thanks. ...

What should Linux/Unix 'make install' consist of?

I've written a C++ program (command line, portable code) and I'm trying to release a Linux version at the same time as the Windows version. I've written a makefile as follows: ayane: *.cpp *.h g++ -Wno-write-strings -oayane *.cpp Straightforward enough so far; but I'm given to understand it's customary to have a second step, make...

Makefile generators: premake vs bakefile?

For my C++ build process, I am using Bakefile, a nice little Makefile generator, which lets you specify your build targets in XML, and it can generate various Makefiles or project files from it. It works fine and I use it to generate the GNU autotools scripts. Now I heard of Premake, which seems to have a similar functionality. You spe...

Will the ".target-name" targets in make files always run?

I'm new to make and makefiles, so forgive me if this is very basic. I'm looking through some makefiles in my project and I'm seeing 2 types of targets -- targets that don't begin with a . character and targets that do. And from what I'm guessing, it seems like the ".target-name" targets are always executed, is my assumption true? I did...

Eclipse CDT and unknown tags

Currently we are looking at moving our development environment from CodeWright (which has long since been abandonned by Borland) and moving to Eclipse. We are using Eclipse for Perl, PHP and some Windows C++ development with much success. The issue comes up however with our embedded environment which uses - in the makefile - some defi...

Equivalent of Make on Windows?

I develop on Windows, and I'd like to use beanstalkd. It's only available as a tarball, and I was just wondering if there is some way to easily build it like you can in Linux? I found some ports of gnu make for Windows, but they don't seem to be working. Are the source distributions somehow specific to Linux? Edit: When I try to use min...

how to have make targets for separate debug and release build directories?

Hi all, I am looking for suggestions to properly handle separate debug and release build subdirectories, in a recursive makefile system that uses the $(SUBDIRS) target as documented in the gnumake manual to apply make targets to (source code) subdirectories. Specifically, I'm interested in possible strategies to implement targets like...

reevaluate makefile variables

Is there a way to reevaluate a variable's definition upon each use? For example: MAP_FILES = $(shell find $(TMP) -name "*.map") all: generate_map_files work_with_map_files generate_map_files: ./map-builder work\_with\_map_files: $(MAP_FILES) ./map-user %.map: ./map-edit $@ So, MAP_FILES will be evaluated when the makefile...

How do I check dependencies when invoking a sub-make to build when there are changes?

If I have a makefile that calls another makefile, how to I get the master makefile to correctly check if the dependencies of the subordinate makefile have changed? For example, if I have the rule server: @cd $(SERVERDIR) && $(MAKE) That invokes make in the subdirectory in which I build an executable "server". However, if I chang...

Simple Makefile Problem (with a simple dependency)

Hi all, I have 4 '.cpp' files and 1 header files: Tools.cpp Code1.cpp Code2.cpp Code3.cpp and Tools.hh Now all Code1.cpp, Code2.cpp, Code3.cpp use functions stored in Tools.cpp. Currently, what I do to compile all of them is using this simple shell script: #!/bin/bash echo "compiling Code1.cpp"; g++ Code1.cpp Tools.cpp -o Code1 e...

Makefiles on windows with g++, linking a library

Hi, I've gotten fed up with MSVC++6 and how everyone is always telling me that it's a crappy compiler and such.. So now I've decided to try to use vim plus g++ and makefiles. Anyway here's my problem.. I have the following makefile # This is supposed to be a comment.. CC = g++ # The line above sets the compiler in use.. # The next li...

How can I automatically create (and remove) a temp directory in a Makefile?

Is it possible to have make create a temp directory before it executes the first target? Maybe using some hack, some additional target etc.? All commands in the Makefile would be able to refer to the automatically created directory as $TMPDIR, and the directory would be automatically removed when the make command ends. ...

How can I use bash syntax in Makefile targets?

I often find bash syntax very helpful, e.g. process substitution like in diff <(sort file1) <(sort file2). Is it possible to use such bash commands in a Makefile? I'm thinking of something like this: file-differences: diff <(sort file1) <(sort file2) > $@ In my GNU Make 3.80 this will give an error since it uses the shell instead...

Good techniques to use Makefiles in VisualStudio?

I know the ideal way to build projects is without requiring IDE based project files, since it theoretically causes all sort of trouble with automation and what not. But I've yet to work on a project that compiles on Windows that doesn't depend on the VisualStudio project (Ok, obviously some Open Source stuff gets done with Cygwin, but I'...