risc

Small RISC emulator.

I'm looking to build a VM into a game and was wondering if anyone knew of any really simple VM's (I was thinking RISC/PIC was close to what I wanted) that are usually used for embedded projects such as controlling robots, motors, sensors, etc. My main concern is having to write a compiler/assembler if I roll my own. I'd be nice to use th...

Do x86/x64 chips still use microprogramming?

If I understand these two articles, the Intel architecture, at it's lowest level, has transitioned to using RISC instructions, instead of the the traditional CISC instruction set that Intel is known for: http://www.hardwaresecrets.com/article/235/4 http://www.tomshardware.com/reviews/intel,264-6.html If that's the case, then are x86/x64...

Branchless memory manager?

Anyone thought about how to write a memory manager (in C++) that is completely branch free? I've written a pool, a stack, a queue, and a linked list (allocating from the pool), but I am wondering how plausible it is to write a branch free general memory manager. This is all to help make a really reusable framework for doing solid concur...

Any ideas for developing a Risc Processor friendly string allocator?

I'm working on some tools to enable high throughput data-oriented development, and one thing that I've not got an immediate answer for is how you go about allocating strings quickly. On risc processors you've got another problem of implementation that the CPU doesn't like branching, which is what I'm trying to minimise or avoid. Also, ca...

How can I perform 64-bit division with a 32-bit divide instruction?

This is (AFAIK) a specific question within this general topic. Here's the situation: I have an embedded system (a video game console) based on a 32-bit RISC microcontroller (a variant of NEC's V810). I want to write a fixed-point math library. I read this article, but the accompanying source code is written in 386 assembly, so it's nei...