makefile

Generating RC dependencies

I have a fairly large project which uses make for its build infrastructure. When we perform a build, we take advantage of cl.exe's /showInclude option to find source dependencies. Is there a similar capability for rc.exe? The basic problem is this: A makefile specifies a resource to be compiled (say, resources.rc). The resource file in...

What is the reasoning behind the Makefile whitespace syntax?

G'day, I'm revisiting Python after Michael Sparks's excellent walkthrough of Peter Norvig's Python spell checker at the SO DevDay in London. One of the points he highlighted was how clean Python is to look at. Not cluttered with braces for scopes but using white space to indicate block scope instead. This got me thinking. I wonder if ...

File or directory not found in eclipse c++ project in linux even after including all the paths. Why?

I have the source code of a project that has been done in C++ eclipse in linux platform and i want to change a small value in one of the port related things. So I tried to build it in eclipse in fedora by File -> New ->Standard Make C++ Project. So many inclusion errors came and I got rid of it by doing Project -> Properties -> C/C++ Inc...

multi package makefile example for go

I'm trying to setup a multi package go project something like ./main.go ./subpackage1/sub1_1.go ./subpackage1/sub1_2.go ./subpackage2/sub2_1.go ./subpackage2/sub2_2.go where main.go imports both subpackage1 and subpackage2. And subpackage2 imports subpackage1. Ive been looking around for go makefile examples but I can't find anyth...

makefile: how to show line numbers for debugging?

Is there a way to have make display the line number where it declares an error? The -d switch doesn't seem to cut it. Updated: Example output: Reaping winning child 0x08aa8648 PID 9381 /bin/sh: Syntax error: "then" unexpected (expecting "fi") ...

make: is there a way to wrap a command shell section?

In a makefile, is there a way to "wrap" a section of shell commands in order to save on the line continuation \ all the time? updated: my main area of concern revolves around stuff like nested if blocks. @if ... \ #do stuff \ else: ; \ #do some more stuff \ @if ... \ # do more stuff ... ...

CMake: How to generate different shared library names depending on build type

This is my first time using CMake and I'm trying to build QJSon, a JSON parser for Qt 4.x. What I want basically is to build different output library names depending on the build configuration. I'm using ${CMAKE_BUILD_TYPE} macro to generate different targets (qjson.lib/qjson.dll and qjsond.lib/qjsond.dll). Seems that the VS 2008 solutio...

Which open-source project can be used a 'showcase' for mid-size project MAKEFILE management?

hi, guys now i need to design/organize the source-code structure and makefiles for the next project. This is a software implemented largely by C++ and supposed to be used normally on Linux. It will include following components: projecthome/3rd_party_lib_boost/ hdr and src projecthome/3rd_party_lib_from_vendor/ hdr and src # libraries ...

what's wrong with my makefile?

I have this project that that I compile with the following command: g++ ALE.cpp -lncurses This gives me a.out file. I have the following Makefile but it seems to not be edited correctly. HEADERS = LinkedListNode.h LinkedList.h Classes.h GUI.h Functions.h default: ale ale.o: ALE.cpp $(HEADERS) g++ -c ALE.cpp -o ale.o -lncurses ...

Build system for a highly modular portable open source project

We have an Open Source software project in the very beginning. The program is thought to be highly modular: for example, the underlying database can be either sqlite, postgre, or berkley, depending on the preferences of the end-user. Only one systematic approach I'm confident with, is to use Autotools (GNU build system). I would like to...

Does the Visual Studio C compiler have an equivalent to GCC's -M?

I would like to automatically generate a Makefile dependency list, but I am using Visual Studio 2005. If I were using GCC, I could pass -M (or one of the many variants) to create this dependency list. Looking through the command line options to cl.exe, I don't see anything obvious. I can handle tweaking the output with post-processing,...

how to write cd command in makefile

for example I have something like this in my makefile all: cd some_directory but when I type make I saw only 'cd some_directory' like in echo command ...

How does make know which files to update

I noticed that when I make changes to some files and then I type make, it will run certain commands related to those files. If I don't change anything, then make doesn't do anything, saying that the program is up to date. This tells me that make has a way of knowing which files were changed since it was last run. How does it know? It...

how to export headers using Qt pro files

I've a project with following files TestProject/api/apiheader1.h TestProject/api/apiheader2.h TestProject/src/apiimplementaton.cpp TestProject/inc/apiimplementation.h TestProject/TestProject.pro When the project TestProject.pro is built headers apiheader1.h, apiheader2.h needs to be copied to /usr/include/TestLib/. Is it possible to d...

Netbeans re produce Makefile when change options in c/c++ developing

I create new c/c++ project in Netbeans and change Makefile and add -lpthread for work with pthread and run my project .also I need to add some runtime argument from project properties/Run/Arguments . when I change runtime Arguments Makefiles that place at /'project folder'/nbproject/private/Makefile-Debug.mk & Makefile-Release.mk are re ...

Can you create custom build rules for XCode based on file type?

I have a project with a bunch of .png files that I want to convert to PVRTC compressed textures. Right now, I'm using a custom XCode run script phase that looks like this: TEXTURE_TOOL=/Developer/Platforms/iPhoneOS.platform/Developer/usr/bin/texturetool $TEXTURE_TOOL -e PVRTC --bits-per-pixel-2 -o "$SRCROOT/images/select_menu_bgs1.pvr...

Makefile: ifeq directive compares special variable to constant does not work

Hi're, I have a little issue with my Makefile. I want make to change commands regarding the working directory. I added a conditionnal directive to the rule testing the current target's directory ($(*D)). The thing is that make always goes to the second branch of my test, even when my file is in mySpecialDirectory and echo indeed prints...

How exactly do I use a makefile?

I'm really confused at the moment. So I have 5 files: main.c, flight.c, flight.h, passenger.c, and passenger.h flight.h has function prototypes for flight.c, and passenger.h has function prototypes for passenger.c flight.c and passenger.c have definitions for these functions. main.c is the program I'll interact with, calling function...

include stdio makefile

Im trying to use the sprintf() function. Therefore I has to include the stdio.h in my C project. If I compile the project without including the stdio.h in my makefile, the compiler generates the error that sprintf() is a unknown function. Including the stdio.h to the makefile generates the error that there is "no rule to make target." ...

Is there a tool to automatically convert a make file to sln/vcproj?

Google reveals many tools for taking Visual Studio format sln/vcproj files, and producing a make file from them. But I can't find one that solves the opposite problem - I have a make file that references hundreds of .c and .h files and (for convenience, for debugging, for writing code in the VS IDE) would like to open it as a Visual Stud...