makefile

arithmetic in a Makefile

Is it possible to perform some operations on variables in a Makefile. For instance, defining JPI=4 JPJ=2 Is it possible to define in the same Makefile a variable JPIJ equal to the expanded value of $(JPI)*$(JPJ) ? ...

debugging a makefile

I have a makefile which has statements like below: TOPICS = dmic SRV_MODE = ifeq "$(SRV_FLAG)" "ON" SRV_MODE = 2 endif vpath d%_srv.h $(CNT_PATH) USER_PRE_TARGETS := $(foreach topic,$(TOPICS),$(topic)_srv.h) dmic_srcs = $(wildcard $(CCWSCA)/dmic/src/*.c) \ $(wildcard $(CCWSCA)/dmic/src/*.ppc) dmic_srv.h: $(dm...

What is currently the best build system.

A few years ago I looked into using some build system that isnt Make, and tools like CMake and SCons seemed pretty primitive. I'd like to find out if the situation has improved. So, under the following criteria, what is currently the best build tool: platform agnostic: should work on windows, linux, mac language agnostic: should have b...

How to convert a makefile into readable code?

I downloaded a set of source code for a program in a book and I got a makefile. I am quite new to Linux, and I want to know whether there is any way I can see the actual source code written in C? Or what exactly am I to do with it? ...

How to generate Debug symbols with Makefile for C? [Linux]

Hi I'm trying to use GDB and KDEvelop to debug a console app under Knoppix VM. KDevelop and GDB don't break at my breakpoints. I suspect it's because they don't have debug symbols. If I'm correct how do I need to change my Makefile to create those. Maybe the problem is somewhere else? Regards, Ariel ...

mod_wsgi on Snow Leopard python version mismatch

Hello, I'm trying to run mod_wsgi 3.1 under Apache 2.2.14 using a non-default python installation on Mac OS X 10.6. After downloading the mod_wsgi source I run: sudo apachectl -k stop then ./configure --with-python=/usr/local/Cellar/python/2.6.4/bin/python make sudo make install I then start up apache again sudo apachectl -k sta...

Create directories using make file

Hi all, I'm a very new to makefiles and i want to create directories using makefile. My project directory is like this +--Project +--output +--source +Testfile.cpp +Makefile I want to put all the objects and output into the respective output folder. I want to create folder structure which would be like this afte...

Makefile, Pattern-Rules and Directories.

I want to write a (gmake) makefile for a compiler that - unlike gcc - puts all output files into a specific directory. Unfortunately this behavior cannot be changed. My sources are in multiple directories. How do I write a pattern-rule that lets me compile the sources. Okay, that's a bit unclear. Here is an example. My sources look may...

Error in linking to friend functions

I have a class 'Vector3' which is compiled successfully. It contains both non-friend and friend functions, for example, to overload * and << operators when Vector3 is the second operand. The problem is I can't link to any of the friend functions, be it operator overloaded or not. So I can confirm that the error is not specific to operato...

Building my project with make

I'm working to improve the long languishing Linux build process for Bitfighter, and am having problems with make. My process is actually quite simple, and since make is (nearly) universal, I want to stick with it if I can. Below I've attached my current Makefile, which works, but clumsily so. I'm looking for ways to improve it, and ha...

Problem generating dependencies in Makefile using -MM

Hi, I am new to Makefiles and g++ and i am struck with a problem while generating dependencies of the project files using -MM flag. I'm posting the Makefile i am using for your consideration. Please take a look. OUTPUT_ROOT := output/ SOURCE_ROOT := source/ TITLE_NAME := TestProj SOURCES := \ MyFile.cpp \ stdAfx.cpp \ Main.cpp \...

Generate all project dependencies in a single file using gcc -MM flag

Hi all, I want to generate a single dependency file which consists of all the dependencies of source files using gcc -M flags through Makefile. I googled for this solution but, all the solutions mentioned are for generating multiple deps files for multiple objects. DEPS = make.dep $(OBJS): $(SOURCES) @$(CC) -MM $(SOURCEs) > $(DEP...

Reuse makefile rule

I'm learning makefiles and I'm trying to figure out how to reuse a rule. Right now I have the following: CPP = cl CPPFLAGS = /Od /D "WIN32" /D "_CONSOLE" /D "_UNICODE" /D "UNICODE" /Gm /EHsc /RTC1 /MDd /Fo"Debug\\" /Fd"Debug\vc90.pdb" /W3 /nologo /c /ZI /TP /errorReport:prompt .SUFFIXES: .exe .cpp Exercise35.exe: $(CPP) Exercise3...

Makefile define: recursive expansion question

In a makefile, I define a variable using the define directive. This variable will hold a configurable list of commands that I want to execute. I would like this variable to get a list of files (.foo files, for example). These files are created during the makefile execution. For example makefile: MY_VAR = $(wildcard *.foo) define MY_VAR...

Makefile question in OpenWRT build system

The following code is taken from OpenWRT project. Can someone give an abstract description? Thanks in advance! # # Copyright (C) 2007 OpenWrt.org # # This is free software, licensed under the GNU General Public License v2. # See /LICENSE for more information. # SUBTARGETS:=clean download prepare compile install update refresh prereq d...

Concatenation of foldername and filenames in nmake

I have a Makefile for Nmake containing a list of files in a macro: MYSRCFILES1=myfolder\file1.svg myfolder\file2.svg ... myfolder\file99.svg and a second one just like this: MYSRCFILES2=myfolder2\file1.svg myfolder2\file2.svg ... myfolder2\file99.svg What I am trying is to avoid duplication of the list of files, and to avoid duplic...

Generate VS Solutions and Projects From a Given MakeFile

I downloaded a few open source c++ projects from the internet, which makes use of makefile for compilation purpose. Is there anyway to import those makefiles into the VS 2008, make VS 2008 to use the makefiles to generate binaries? ...

Get MakeFile Directory

I am distributing my cpp files along with a makefile. Now the makefile is located in the same directory as the cpp file. What is the variable ( if any) in makefile that allows me to retrieve the current directory with the makefile is located? In this way I can use that variable to specify my cpp path for compilation. My makefile is as...

How can I create a time-based Makefile rule?

I would like to have a Makefile target that gets rebuilt only if the target file is older than some time interval. As an example, say that I have some way of generating a key that is valid for one day, but generating it takes a non-trivial amount of time. I could just regenerate it each time I needed it: .PHONY: key key: sleep 5 &...

What Does *.o/.Suffixes in Makefile Mean?

I have seen commands like this all over Makefiles, which I don't quite understand: vpath.o: make.h config.h getopt.h gettext.h dep.h and .SUFFIXES: .SUFFIXES: .f .o # # %------------------% # | Default command. | # %------------------% # .DEFAULT: @$(ECHO) "Unknown target $@, try: make help" # # %------------------------------...