Hi, I'm making a Makefile that moves an output file (foo.o) to a different directory (baz). The output file moves as desired to the directory. However since make won't recompile the output file if I type 'make' again, mv gets an error when it tries to move the non-existent empty file to the directory baz. So this is what I have defined...
I have a makefile: #Nice, wonderful makefile written by Jason CC=g++ CFLAGS=-c -Wall BASE_DIR:=. SOURCE_DIR:=$(BASE_DIR)/source BUILD_DIR:=$(BASE_DIR)/build TEST_DIR:=$(BASE_DIR)/build/tests MAKEFILE_DIR:=$(BASE_DIR)/makefiles DATA_DIR:=$(BASE_DIR)/data DATA_DIR_TESTS:=$(DATA_DIR)/tests MOLECULE_UT_SOURCES := $(SOURCE_DIR)/molecule_tes...
Hi, I'm wondering how I can avoid some echo in a Makefile : clean: rm -fr *.o this rule will print : $>make clean rm -fr *.o $> How can I avoid that? thx! ...
I would like to know how to do something in ant(1) that's equivalent to a particular makefile(4) rule. The makefile(4) rule does the following: 1) starts a process that doesn't terminate and that writes one line to its standard output stream; 2) reads the line from the process; 3) constructs a file using the line; and 4) starts a second...
Hi, I have written 3 .sqc files i.e. embedded sql in host language C. I need to make a (Unix) shell script to simply compile all 3 sqc files in a row. How can I do that? Right now, I can individually run each .sqc file using a Makefile that basically converts the .sqc file to a c file and then compiles it. Can I make 3 individual Makef...
I have a small project that builds a number of targets from the same source files. The targets require building the source files with different compile flags. This is actually on cygwin so I'll use that as the concrete example although I suppose this is a generic problem. So this would be an example Makefile: a: CFLAGS = a: a.o c.o b...
I have some template classes I've written that are dependencies for several other classes I need to compile. I have a few options as to how I can do this in my Makefile: Each class that requires a template lists its template requirements. This has the drawback of needing to recreate the dependency tree every time I want to add a new c...
Hello. I'd like to build my own GNU/Linux system from scratch using cross-compilation (just like the CLFS project). Most of the packages I would use are distributed with a configure script, and you just have to run it with the right arguments. For various reasons, I'd like to skip this step, and run make instead. Of course I need a custo...
I just discovered GNU make's $(foreach) function, and I'm following the foreach-eval-call pattern used in the documentation; for instance, graphviz_progs := dot neato circo fdp define LAYOUT_template %-$(1).dot: %.dot $(1) -Tdot $$? > $$@ endef $(foreach p, $(graphviz_progs), \ $(eval $(call LAYOUT_template,$(p))) \ ) This works...
I have generated my autoconf/automake files for my project. So far eveything works fine when I issue the ./configure && make && make install, however, when I do ./configure on some other machine, I get configure: error: cannot find install-sh or install.sh in "." "./.." "./../.." If I ls -la on the source directory where I generated the...
From the command line you can make multiple directories like so: mkdir -p build/linux/{src,test,debug} How can the same thing be achieved from a Makefile? I've come up with this: # The architecture/OS to compile for ARCH := linux # Object files go here, under the architecture/OS directory BUILD_DIR := build/$(ARCH) # Lis...
I have a large makefile which builds several libraries, installs them, and then keeps on building objects which link against those installed libraries. My trouble is that I want to use "-lfoo -lbar" as g++ flags to link against the two installed libraries, but the dependencies get messed up. If I change a header "42.h" which the librar...
I am writing a generic makefile to build static libraries. It seems to work well so far, except for the line calling sed: # Generic makefile to build a static library ARCH = linux CFLAGS = -O3 -Wall SOURCES = src BUILD_DIR = build/$(ARCH) TARGET = $(BUILD_DIR)/libz.a CFILES = $(foreach dir,$(SOURCES),$(wildcard ...
Hi, I've just inherited some C++ code which was written poorly with one cpp file which contained the main and a bunch of other functions. There are also .h files which contain classes and their function definitions. Until now the program was compiled using the command "g++ main.cpp". Now that I've seperated the classes to .h and .cpp f...
How to get the invoking target of the gnu makefile? for example, I invoke the makefile with the following command line: make a-target How can I get the invoking target "a-target" in the makefile to assign it to a variable? further more, if more than one target is specified in cmd line: make target1 target2 ... How to get all of the...
Hey I managed to compile the sqlitejdbc from here. The instructions in the MakeFile there says: Makefile for the native SQLite JDBC Driver No auto-goop. Just try typing 'make'. You should get two interesting files: build/TARGET_OS/LIBNAME build/sqlitejdbc-vXXX-native.jar To combine these, type: cd build mv LI...
I would like to display the explicit path to a library which will be used in the linking stage of compilation. I want to do this so that I can add the library as a dependency to a separate object file. In other words, I often link using: g++ myFile.cpp -Lsomewhere -Lelse -Lhere -Lthere -lfoo Is there a way to coerce g++, ld, ldd, or ...
I have the following block of code in a makefile: param_test_dir: @if test -d $(BUILD_DIR); then \ echo Build exists...; \ else \ echo Build directory does not exist, making build dir...; \ mkdir $(BUILD_DIR); \ fi @if test -d $(TEST_DIR); then \ echo Tests exists...; \ else \ echo Tests directory does not e...
Hi Everyone, I've been heavily refactoring my makefiles, with help from Beta, Paul R, and Sjoerd (thanks guys!). Below is my STARTING product: #Nice, wonderful makefile written by Jason CC=g++ CFLAGS=-c -Wall BASE_DIR:=. SOURCE_DIR:=$(BASE_DIR)/source BUILD_DIR:=$(BASE_DIR)/build TEST_DIR:=$(BASE_DIR)/build/tests MAKEFILE_DIR:=$(BASE_D...
I recently switched from using Makefiles to using Automake, and I can't figure out how to write the following simple if statement using automake: DEBUG ?= 1 ifeq (${DEBUG},1) CXXFLAGS:=$(CXXFLAGS) -g else CXXFLAGS:=$(CXXFLAGS) -O3 -DNDEBUG endif Is this even possible to do if I'm using automake? Since it generates the makefile from au...