I can't figure out a way to define a generic pattern rule for the following kind of production with make: require xyzzy-en_US.ext2 from xyzzy.ext0 via xyzzy.ext1. This works: all: xyzzy-en_US.ext2 # to be compiled from xyzzy.ext0 %.ext1 : %.ext0 # produce xyzzy.ext1 %-en_US.ext2 : %.ext1 # produce xyzzy-en_US.ext2 But how to g...
I need to have a makefile work under DOS (Windows) and Cygwin. I having problems with the makefile detecting the OS correctly and setting appropriate variables. The objective is to set variables for the following commands, then invoke the commands in rules using the variables: Delete file: rm in Cygwin, del in DOS. Remove director...
I like to keep my Makefiles flexible and multifunctional. One of the tasks I usually add to make command is tar, for example the following instruction does the job: tar: tar -cvf $(PROGNAME).tar $(SRCS) Makefile My question is: How can CMake be used to generate personalized commands like tar? I would like to see some code samples....
I needed to add AM_PATH_CHECK to configure.am I then try to run the usual sequence of autotools commands to rebuild all the makefiles and whatnot: aclocal automake -ac autoheader autoreconf ./configure make and here my lack of understanding of autotools showes up because this release of openssh has no Makefile.am??? now what do I do? ...
How can I tell the linker that statically link libfoo.a while building the shared object sharedobj.so using gcc/make. I have tried to pass the LDFLAG options LDFLAGS += -W1 --whole-archive -L/path/to/libfoo -lfoo I have also tried to pass LDFLAGS the options LDFLAGS += -W1, static -L/path/to/libfoo -lfoo I have also tried to pass LD...
a linker receives obj's and lib's to create exe's or other libs. But so does a makefile(but it can start from sources on top of that). what is the difference between the two? ...
Dear gurus, Please consider the following Makefile: CC = g++ CFLAGS = -c -O -Wall EFLAGS = -O -Wall -lm -o UTILITIES = error.o stream_manip.o mat_ops.o GaussElim.o UTILITIES += abstractmatrix.o dvector.o dmatrix.o ConjGrad.o # All objects %.o: %.cpp %.hpp $(CC) $(CFLAGS) $< # Executables (doesn't have extension) % : %.cpp $(...
Given the line: program_OBJS := ${program_SRCS:.cpp=.o} I would like to append .o to each filename instead of replacing .cpp with .o. How do I do that? ...
Lets say I have files: Libs: one.cpp, one.h two.cpp, two.h three.cpp, three.h Program: program.cpp Is there way, to create Makefile which will compile only that *.cpp which were modified from last compilation? Currently I have something like that: SRCS = one.cpp two.cpp three.cpp OBJS = $(SRCS:.cpp=.o) all: $(OBJS) program ....
I have build my code for two different platforms at once using two different compilers and libraries. How can I do this with single make file. Currently my makefile contents are given below. How can instruct it to change the compiler to gcc with in the same make file VPATH = /root/Documents/project/src CROSS_COMPILE = /opt/compilers...
I am running Windows 7 with gcc/g++ under Cygwin. What would be the Makefile format (and extension, I think it's .mk?) for compiling a set of .cpp (C++ source) and .h (header) files into a static library (.dll). Say I have a variable set of files: file1.cpp file1.h file2.cpp file2.h file3.cpp file3.h .... What would be the makefile...
I have the following recursive makefile: .PHONY: all clean %.subdir: $(MAKE) -C src $* $(MAKE) -C dict $* all: all.subdir clean: clean.subdir and it works fine: $ make all make -C src all make[1]: Entering directory `/or-1.3.6-fix/src' make[1]: Nothing to be done for `all'. make[1]: Leaving directory `/or-1.3.6-fix/src' ma...
I would like to perform expansion on a variable that might contain references to other variables. I'll illustrate with an example: a = 1 b = 2 c = 3 X = foo bar baz $(foreach x, a b c, $$(value $(x))) qux $(info $(X)) If you run this makefile, it prints: foo bar baz $(value a) $(value b) $(value c) qux I'd like to know how to expand ...
I have a directory images/ that I want to copy to build/images/ from within a Makefile. The directory might contain multiple levels of subdirectories. What would be the most elegant way to do that? I want: avoid a full directory copy on each make run (i.e. no cp -r) guaranteed consistency (i.e. if a file changed in images/ it should be...
I'm using Make and I have a makefile which sets a variable with a value that I need to override from a parent makefile. I've tried setting the variable in the parent makefile and using export to pass it to the submake but the variable is not using the passed down value, instead it is using the value explicitly set in the sub-Makefile. ...
The problem arises when makefile needs be run on different OS and various setting should be properly set up (escaping, path separator, etc) depending on OS. The first approach was to use Windows COMSPEC: ifneq ($(COMSPEC)$(ComSpec),) ## in windows else ## in linux endif This is false positive for Cygwin, because it sees Windows' env...
I have a directory with 50 .c source files and each one of these .c files depends on a .h file with the same name plus a common header file. Example: foo.c depends on foo.h and common.h bar.c depends on bar.h and common.h baz.c depends on baz.h and common.h Is it possible to setup this dependency without having to make a separate tar...
Hi All, I'm writing a makefile for a project. The project makes use of OpenCV. I have installed the OpenCV 2.1, now, how can I include the OpenCV libraries into the makefile? When I had the same project in a non-makefile type project environment, I used to point to these libraries in the Project Properties of Eclipse. As given below - ...
Hi All, I'm having a hard time writing makefiles. I have experience in using the extern variables, when I build the project without using makefiles I get absolutely no errors and I can run the program. But from the time I wrote the makefile to build the project, I'm getting undefined reference to errors. I have more than 3 files with ...
I have tried putting the following in my Makefile: @if [ $(DEMO) -eq 0 ]; then \ cat sys.conf | sed -e "s#^public_demo[\s=].*$#public_demo=0#" >sys.conf.temp; \ else \ cat sys.conf | sed -e "s#^public_demo[\s=].*$#public_demo=1#" >sys.conf.temp; \ fi but when I run make, I get the following error: sed: -e expression #1, char ...