How to undo ./configure command
Hi, Is there a command that removes all the files created by the ./configure command of libxml2?? Thanks Samuel ...
makefile
How to check value of defined symbols (Eclipse->Paths & Symbols) in a makefile?
We have a project that used to be an Eclipse-managed CDT project. However, I am trying to change it to a standard makefile project. One of them has a couple of symbols defined in Project Properties->C/C++ General->Paths & Symbols->Symbols. The makefiles generated by Eclipse used to automatically get the value when it was managed. Th...
Make GNU make use a different compiler
How can I make GNU Make use a different compiler without manually editing the makefile? ...
pretty print makefiles
The linux kernel (and various other projects including git) have very nice makefiles that hide the giant cc calls into nice little acronyms. For example: gcc -O2 -o cool.o cool.c -llib gcc -O2 -o neat.o neat.c -llib would become: CC cool.c CC neat.c Which is really nice if you have a project with a large number of files and long c...
GNU Makefile rule generating a few targets from a single source file
I am attempting to do the following. There is a program, call it foo-bin, that takes in a single input file and generates two output files. A dumb Makefile rule for this would be: file-a.out file-b.out: input.in foo-bin input.in file-a.out file-b.out However, this does not tell make in any way that both targets will be generated s...
Does Visual Studio 2008 use make utility?
I have checked in buid directory and have not found makefile there. How does Visual Studio 2008 buid the project? Does it use makefile? ...
rm -rf versus -rm -rf
Hello, In a Makefile, I read: -rm -rf (instead of rm -rf). What does the first "-" mean at the beginning of the line in a Makefile ? Regards, Apple92 ...
ede-proj-regenerate does weird things with my Makefile
Hi, I have created a really basic project (Make) like this: (ede-proj-project "zrm" :name "zrm" :file "Project.ede" :targets (list (ede-proj-target-makefile-program "zm" :name "zrm" :path "" :source '("zrm.c") ) ) ) When doing M-x ede-proj-regenerate RET and M-x compile RET RET (accepting make -k as my c...
How to match occurance of word in list in makefile
I wonder how to match exact occurrence of a given word in the given list of words using only standard makefile operations. In the below example for WORD_TO_MATCH = a the result is positive and apparently wrong. INPUT_LIST= aa bb WORD_TO_MATCH = aa #WORD_TO_MATCH = a ifneq ($(findstring $(WORD_TO_MATCH),$(INPUT_LIST)),) $(warning ...
Build multiple executables with small changes in objects
Consider the following Makefile COMP = compiler OBJECTS = file1 \ file2 \ file3 \ file4 \ file5_suffix \ file6 \ file7 \ file8 \ file9_suffix \ file10 all: $(OBJECTS) $(COMP) $(OBJECTS) -o bin/executable_suffix Is there an easy way to compile multi...
Makefile patsubs double replacement
hello. is a possible to do something like this, without shell command: CXX_MODULES += $(patsubst %, %/%.cpp, $(LIBRARIES)) notice double replacement which does not work (only first replacement happens) after some tinkering I came up with $(join $(LIBRARIES), $(patsubst %, /%.cpp, $(LIBRARIES))) Thank you ...
Generate multiple target using single action/rule
How do I write a rule to generate set of files using a single action. Example: Files x, y, z are generated as a result of single execution of script t.sh which takes file a as input. x y z: a t.sh $@ GNU make tries to execute t.sh 3 times. ...
Default rules in Make
Is there a mechanism in make to allow for default global implicit rules that are available anywhere, similar to the built-in rules? Make provides some built-inimplicit rules for compiling C/C++/Fortran files, without even requiring a Makefile for simple cases. However, when compiling other languages (e.g. Go programming language files)...
How to write different implicit rules for different file names for GNU Make
Hi! I have a directory in which I keep adding different C++ source files, and generic Makefile to compile them. This is the content of the Makefile: .PHONY: all clean CXXFLAGS = -pipe -Wall -Wextra -Weffc++ -pedantic -ggdb SRCS = $(wildcard *.cxx) OBJS = $(patsubst %.cxx,%.out,$(SRCS)) all: $(OBJS) clean: rm -fv $(OBJS) %.out:...
GNU Makefile: multiple outputs from single rule + preventing intermediate files from being deleted
This is sort of a continuation of question from here. The problem is that there is a rule generating multiple outputs from a single input, and the command is time-consuming so we would prefer to avoid recomputation. Now there is an additional twist, that we want to keep files from being deleted as intermediate files, and rules involve wi...
Managing complex Make-based project tree in Eclipse
I have a very complex source tree containing multiple projects for multiple platforms, all managed by several makefiles. The most obvious problem to me is that Eclipse wants .project files at the root of all the project's files. My tree structure is something like this: Makefile (recursively makes foo, bar, baz and biff) arm/ arm/lib/.....
How to create dependencies in automake?
Hello, I have a Makefile.am file right now that looks like this: lib_LIBRARIES = foo.a foo_a_SOURCES = bar.F90 baz.F90 When compiled, bar.F90 gives bar.o. However, bar.F90 depends on several other Fortran files (cat.F90, dog.F90, pig.F90). I want to set up Automake to rebuild bar.o if the source of one of these dependencies change. ...
Commands implicitly threaded in Makefiles ?
Hi, I have a "super" makefile which launches two "sub" make file: libwebcam: @echo -e "\nInvoking libwebcam make." $(MAKE) -C $(TOPDIR)/libwebcam uvcdynctrl: @echo -e "\nInvoking uvcdynctrl make." $(MAKE) -C $(TOPDIR)/uvcdynctrl uvcdynctrl uses libwebcam... I noticed that those two builds are launched ...
Compiling C Source with Makefile in Windows
I'm trying to compile a downloaded program in Windows. The program is usually run in Linux, but is programmed to also run in Windows (the code has #if defined(_WIN32)'s in it, and claims to work with borland free tools). When I try to use make from the command line, it tells me "Incorrect command line argument: -C". In the makefile, t...
How to organize makefiles / solutions etc. in multiplatform projects?
I have a project which can be compiled with Visual Studio, GCC and with some embedded compilers. Sources are shared, but each platform requires separate makefiles, project files, solutions etc. There are two ways I can organize them: Intermixed in a single hierarchy of folders With separate folders for platform-dependent files The fi...