makefile

Skip makefile dependency generation for certain targets (e.g. `clean`)

I have several C and C++ projects that all follow a basic structure I've been using for a while now. My source files go in src/*.c, intermediate files in obj/*.[do], and the actual executable in the top level directory. My makefiles follow roughly this template: # The final executable TARGET := something # Source files (without src/) I...

Makefile : assigning function variable in target command line

I need the xpi_hash variable to be assigned only when update target's command is decided to execute. Then I'm using this variable as environment, exporting, etc.. If I put it outside of rule, it will be expanded firstly, before $(xpi) target is called, hence will not find that file. substitute := perl -p -e 's/@([^@]+)@/$$ENV{$$1} bla ...

using makefile targets to set build options

This is either trivial or runs counter to the philosophy of how make should be used, but I'd like to have a command line that reads as "make debug" rather than "make DEBUG=1". I tried creating a phony target called debug that did nothing except set the DEBUG variable, but then there was a difference between "make debug build" and "make b...

Makefile: ignore prerequisite if does not exist

Is there any way to say that if prerequisite for the given target doesn't exist then ignore that target? For instance, I have the following set of folders chrome_src_folders := $(chrome_src_folder)/content/* \ $(chrome_src_folder)/locale/* $(chrome_src_folder)/skin/* This is where I use it $(jar_path): $(chrome_sr...

makefile: how to call macros in macros

Hello, I have the following macros in my make file: pdf: // do something clean: // just another fancy thing No I want to declare a macro all: which include (or call) the macros above. The following thing doesn't work: all: pdf: clean: I don't want to repeat the code from pdf: and clean: in order not to rebel agains...

makefile problem

Hello I have a problem while trying to run a makefile. I change the path where my java install folder is(C:\Program Files\Java\jdk1.6.0_18\bin), but when I try to run 'make' from my command line I receive : 'make' is not recognized as an internal or external command, operable program or batch file. I need to use makefiles for my curren...

Modifiers in Makefile rule's dependency list

The problem is fairly simple. I am trying to write a rule, that given the name of the required file will be able to tailor its dependencies. Let's say I have two programs: calc_foo and calc_bar and they generate a file with output dependent on the parameter. My target would have a name 'target_*_*'; for example, 'target_foo_1' would be...

makefile compilation problem

I have a problem with a makefile. I have three classes. They do pretty simple stuff. One does an addition on a subtraction, and the last one will instantiate the two and simply print the resulted addition and subtraction. Now when I create my makefile, I compile my Plus.java and my Minus.java but don't know how to compile the main class...

What is wrong in this simple Makefile

SRC_VAR = test string for variable manipulation. TEST1_VAR = $(subset for,foo,${SRC_VAR}) all: @echo original str: ${SRC_VAR} @echo substitution: ${TEST1_VAR} This is the output: original str: test string for variable manipulation. substitution: The output should be: original str: My test string for variable manipulatio...

Installing a cpp library on linux

I'm trying to install a library (libspopc), but, when I run the make command, I get the errors: strip libspopc.a libspopc.so strip: 'libspopc.a': No such file strip: 'libspopc.so': No such file make: *** [install] Error Working under the assumption that every version of the library I've tried isn't actually missing two of its files, ...

How do I add dependencies to this header file

Here is a simple header file for six different programs. This Makefile used to work just fine, but then I changed the programs to include other implementation files. This Makefile needs to get changed so that if the implementation files change the files that include those implementation files get recompiled. all: load list show add del...

Make errors - can the gcc compiler warnings prevent a C file from being compiled into an object file?

I'm trying to compile a wireless network card driver for my Linux box and I ran into a problem with the Make command. During the compilation process I normally see warnings on some of the C files that being are compiled; despite the warnings these files were still able to be compiled to an object file. When the Make process comes to a f...

Passing additional variables from command line to make

How to pass variables to gnu makefile from command line arguments? In other words I want to pass some arguments which will eventually become variables in makefile. ...

How to fix this Makefile

Instead of executable code all it does is create files that don't do anything, even if the files are made executable. TARGETS = load list show add delete btree all: $(TARGETS) %: %.cpp g++ $< -g -o $@ -MM -MF [email protected] sed "s/$@\.o:/$@:/" [email protected] > [email protected] -@rm [email protected] DEPS=$(TARGETS:%=%.d) -include $(DEPS) ...

Makefile variable initialization and export

somevar := apple export somevar update := $(shell echo "v=$$somevar") all: @echo $(update) I was hoping to apple as output of command, however it's empty, which makes me think export and := variable expansion taking place on different phases. how to overcome this? ...

How do I create a makefile from a Visual Studio solution file?

I have a Visual Studio project that uses a solution file to build it. I want to generate a makefile so that I can build it using the makefile instead of the solution file. (The reason I need to do this in case you are wondering is that I am incorporating my project into a larger software system that uses makefiles to build, and I want to...

configure.in: AM_DISABLE_SHARED doesn't change my Makefile

I'm extremely new to using Makefiles and autoconf. I'm using the Camellia image library and trying to statically link my code against their libraries. When I run "make" on the Camellia image library, I get libCamellia.a, .so, .la, and .so.0.0.0 files inside my /usr/local/lib directory. This is the command I use to compile my code with th...

How do I build SDL_TTF?

Okay, so I'm on Windows Vista, and I want to use SDL_TTF, but the idiots who made it decided you have to build everything from source, so I to build the .lib files and all that other stuff, but I'm on Windows, so how am I suppose to do this? ...

GNU/Linux developement n00b needs help porting C++ application from windows to GNU/Linux.

Hi! These questions may not be perfectly suited for this site, so I apologize in advance for asking them here. I'm trying to port a computer game from windows to GNU/Linux. It uses Ogre3D,CEGUI, ogreogg and ogrenewt. As far as I know all dependencies work on GNU/Linux and in the game itself there is no ooze-specific code. Here's the q...

Overinclusion of libraries C++

I'm reading about how to put a makefile together, but no-one seems to mention what to do if your files require different sets of libraries, they all seem to use the same set of libraries for each file. Since it seems unlikely that every single file has the same libraries, I take it the list they use must amalgamate all of the libraries r...