makefile

Makefile : Build in a separate directory tree

My project (an interpreted language) has a standard library composed by multiple files, each of them will be built into an .so dynamic library that the interpreter will load upon user request (with an import directive). Each source file is located into a subdirectory representing its "namespace", for instance : The build process has t...

GCC Linking time errors - No rule to make target

Hi Guys, I'm new to the world of Makefile writing. I have a C project which I want to build using GCC and I could write fairly a very good Makefile, which calls 3 other Makefiles, present in different directory structure of the project, recursively, who will then send the respective source files to the GCC compiler. The result of ...

How to run "make install" from Xcode

I have custom Makefile and External build target in Xcode. When I click "Build" it runs "make" When I click "Clear" it runs "make clean" How to run "make install" (or any other target) from Xcode? (btw, this is AVR project and xcode project file was created using avr-project tool shipped with Crosspack-AVR) ...

make always rebuild

My Makefile is: OBJS = b.o c.o a.o FLAGS = -Wall -Werror CC = gcc test: $(OBJS) $(CC) $(FLAGS) $(OBJS) -o test b.o: b.c b.h $(CC) $(FLAGS) -c b.c a.o: a.c b.h c.h $(CC) $(FLAGS) -c a.c c.o: c.c c.h $(CC) $(FLAGS) -c c.c clean: rm a rm *.o all: test If I do make then make again, it always rebuilds 'test'. Why ...

Help in understanding EXPORTS in Makefile.in

Hi, In the Makefile.in of an existing c++ project on linux (ubuntu), it has this: EXPORTS = \ gtkmozembed.h \ gtkmozembed_glue.cpp \ gtkmozembed_internal.h Can you please tell me what does EXPORTS mean? Thank you. ...

Makefile rule without dependency expression

Hi folks! I read the german article about "Make" on Wikipedia and found the following 2 lines: .c.o: $(CC) $(CFLAGS) -c -o $@ $< Why is the dependency expression left out and why does the target use a double file extension? ...

Combining several static archives into a new one

I'm making a game engine for mobile devices. I want to compile my code, link it against a few static libraries and then combine my compiled code with those static libraries to form a new static library. However, my Google Fu is abandoning me. Suppose I have static libraries a.a, b.a and c.a and my code. I want to compile all that into ...

Linux C++: Linker is outputting strange errors

Alright, here is the output I get: arm-none-linux-gnueabi-ld --entry=main -dynamic-linker=/system/bin/linker -rpath-link=/home/oem/android-ndk-r3/build/platforms/android-5/arch-arm/usr/lib -L/home/oem/android-ndk-r3/build/platforms/android-5/arch-arm/usr/lib -nostdlib -lstdc++ -lm -lGLESv1_CM -rpath=/home/oem/android-ndk-r3/build/platfo...

How to create a file using Makefile

Hi, I want to create a .c file from a Makefile. Content of that C file is as follows: char *variable1 = $(VAR1_FROM_MAKEFILE); char *variable2 = $(VAR2_FROM_MAKEFILE); Is it possible? Thanks in advance ...

More GCC link time issues: undefined reference to main

Hi Guys, I'm writing software for a Cortex-A8 processor and I have to write some ARM assembly code to access specific registers. I'm making use of the gnu compilers and related tool chains, these tools are installed on the processor board(Freescale i.MX515) with Ubuntu. I make a connection to it from my host PC(Windows) using WinS...

nmake makefile, linking objects files in a subfolder

My makefile defines a link command: prod_link = $(LINK) $(LINK_FLAGS) -o$(PROD_OUT) $(PROD_OBJS) where $(PROD_OBJS) is a list of object files of the form: PROD_OBJS = objfile1.obj objfile2.obj objfile3.obj ... objfileN.obj Now the makefile itself is at the root of my project directory. It gets messy to have object and listing files...

Legacy C++ project using Makefile ..moving to Eclipse IDE?

I have a legacy C++ project on Linux which uses the typical: ./configure make make install to build and install. I would really like to build it instead with an IDE like Eclipse. Is this doable? Is there something in Eclipse that can parse the original Makefile(s) and turn it into an Eclipse project? ...

Name for build option (for "make install") specifying where to install web application

I want to provide 'install' target for Makefile for web application. I'd like to be able to install it, for example like described below: $ make install \ xxxdir=/var/www/cgi-bin (similarly to how one would use 'bindir' for ordinary programs, and 'mandir' / 'infodir' for documentation). Is there any standard (similar to autotool...

Mercurial - How to stop tracking modified file but keep the first version in repository.

I create the hg repository with my source tree. I want to keep the first version of some files such as Makefile in the repository and then hg don't see it modified even through I modified it. Original problem is that ./configure usually modifies the Makefile but I don't want the build files to committed in the repository. So I want to k...

Makefile to CMakeLists.txt

I have some problems converting the attached Makefile to an equivalent CMakeLists.txt . The build process goes like that : Generate src/lexer.cpp given src/lexer.l.cpp with flex. Generate src/parser.cpp given src/parser.y.cpp with bison. Compile almost anything inside src/ into a .so library. Recompile them with different flags to gen...

GNU make variables in Makefile

Hi, I would like to create a Makefile which also creates a simple script for running the compiled application. I have something like the following: @touch $(SCRIPT) @echo LD_LIBRARY_PATH=$(LIB_DIR) $(APP_DIR)/$(APP) $1 $2 $3 $4 $5 $6 > $(SCRIPT) @chmod +x $(SCRIPT) @echo Script successfully created. And I want $1 $2 ... to appear i...

Compile all C files in a directory into separate programs

Is there a way using GNU Make of compiling all of the C files in a directory into separate programs, with each program named as the source file without the .c extension? ...

Change Makefile variable value

Is there a way to reassign Makefile variable value inside of the target body? What I am trying to do is to add some extra flags for debug compilation: %.erl: %.beam $(ERLC) $(ERLFLAGS) -o ebin $< test: clean debug_compile_flag compile compile_test debug_compile: $(ERLCFLAGS) += -DTEST So if I invoke test target I would lik...

Trying to compile MobileSubstrate addon - Undefined symbol

Hi! I went through this tutorial to create a MobileSubstrate addon. I could compile the example hook without errors. But as soon as I add #import <SpringBoard/SBAwayController.h> in ExampleHookProtocol.h and SBAwayController *awayController = [SBAwayController sharedAwayController]; in ExampleHookLibrary.mm (as the first line of...

Converting Makefile to Visual Studio Terminology Questions (First time using VS)

I am an old Unix guy who is converting a makefile based project over to Microsoft Visual Studio, I got tasked with this because I understand the Makefile which chokes VS's automatic import tools. I am sure there is a better way than what I am doing but we are making things fit into the customer's environment and that is driving my choic...