A question about DRAM organization

Question

My college's lecturer gaves me an assignment and there's a question as follow

A DRAM has 11 multiplexed address pin and one data input/output pin. 14-non multiplexed address pin and 4 data input/output pin Determine the organization of the DRAM

I'm currently stuck on this question,I've been googling for an hour trying to know what is multiplexed address pin and non-multiplexed address pin.Any idea??Thanks if anybody could lend me hand

Answer 1

Multiplexed address pins in the context of DRAM means that you can address a row or a column on the same set of pins. First you'd write the row address to the pins and assert RAS (row address select) to tell DRAM to latch the data for the row. Then you'd place the column address on the pins and assert CAS (column address select) to tell the DRAM to latch the data for the column. At this point, the DRAM will read or write data for that row:column on the in/out pin, depending on what you've told it to do with your R/W select pin.

Non-multiplexed pins mean that the row and column are encoded in the entire address. You write the address, and the DRAM reads or writes a data word at that address.

From this info you can probably figure out the total address space. And your data width is given, right?

Here's a paper that explains multiplexed DRAM in more detail. And if you're still having trouble, you may be able to find more info in What Every Programmer Should Know About Memory, Chapter 2.