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One of the more interesting things I've run into lately is the art and science of laying out chip floorplan and determining packaging for the silicon. I would like to read some materials on the subject for the "Interested Software Guy".

Does anyone have any recommendations (Website or book, so long as it is a good quality)?

+11  A: 

This is a result of my search on the subject as I was curious about your question and this is where I would start myself. Sorry I am not a specialist on the subject but hope it can kick-start you!

Seems floorplan optimization is a matter of combinatorial optimization.

As a developer, you'll want to tackle the theory behind it and most likely some proven algorithms. You might then be interested by books such as:

It's a bit more difficult to get links on this subject, but if you're a member of IEEE Xplore, you might want to look at this paper and other similar ones.

Finally, on the floorplan wikipedia entry, you'll notice this on sliceable floorplans that might give you your best starting point:

Sliceable floorplans have been used in a number of early EDA tools for a number of reasons. Sliceable floorplans may be conveniently represented by binary trees which correspond to the order of slicing. What is more important, a number of NP-hard problems with floorplans have polynomial time algorithms when restricted to sliceable floorplans

Good luck!

lpfavreau
Nice, a hard copy list. Their sure is something to be said for good old bound paper. +1
BCS
It was a pleasure, hope it helps!
lpfavreau
A: 

There seems to be a class on this at Carnegie Mellon

VLSI CAD

some of the lecture notes that looked more interesting than others:

That site make references to one or more books that this fellow published:

Also I found a short tutorial here

BCS
A: 

AutoCAD is a classic... Though on my limited budget I prefer Rhino 2.0.

tsilb