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How would you handle a special case in this digital logic system?

Answer 1

+2 A:

For me, I would tell the user of the FPGA that they must have one of the bits set to 1 on entry.

However, if that's not your preferred solution, what's wrong with the idea of pre-feeding all the Current inputs initially into a big NOR gate (so that the output is true only when all inputs are false). All Current lines also continue through to their AND gates with the exception that Current[1] is OR'ed with the output of our NOR gate before entering it's AND gate

That way, Current[1] would be true entering the AND gate, if all Currents are false.

Keep in mind that I understand boolean algebra but I've never worked on raw hardware - I'm guessing you'll need to buffer all the input signals into the AND gates to ensure correct timing but i suspect you'll know that better than I.

The following diagram is left in in case SO fixes its code/pre blocks - the latest SO update seems to have stuffed them up (leaving them proportional, not fixed-width, font). Anyway, eJames' graphical diagram is better.

Here's my diagram, slightly less elegant than yours :-):

               +-------------------+
               |                   |
               |     +----         |
Current[1]-----+------\   \        |
                       |NOR|o--+   |
Current[2-k]---+------/   /    |   |
               |     +----     |   |
               |              +\   /+
               |              | \_/ |
             +---+            |  OR |
              \ /Buffer        \   /
               +                ---
               |                 |
             +---+             +---+
             |2-k|             | 1 |    <- These signals feed 
             +---+             +---+       into your AND gates.

paxdiablo 2009-01-28 06:10:27

Good solution! The K-input NOR gate can be refactored into an extra OR gate at each bit, which keeps the system modular by number of bits.

e.James 2009-01-28 06:29:41

Also, setting current[1] neatly selects the lowest set bit in the mask as the bit to set in next. I like it :)

e.James 2009-01-28 06:30:40

Is it a requirement for the K+1-bit circuit to be a simple extension of the K-bit circuit? If you're asking for an HDL implementation, you should probably let your synthesis tool do its thing on a behavioral description and constraints; it can usually do a better job than we can.

Matt J 2009-01-28 06:33:51

eJames, I don't understand your refactor comment (educate me :-). You need to treat Current as a *unit* so I can't see how passing *individual* lines will work ??

paxdiablo 2009-01-28 06:35:13

A synthesis tool may also figure out a way to trade off more hardware to shorten the O(K) critical path in the circuit diagram above, if that's advantageous. This is a common technique for priority encoders/schedulers, as they are often the critical path in the larger circuits they schedule.

Matt J 2009-01-28 06:36:11

Or do you mean: replace the buffers with OR gates where the other input is the negated output from NOR?

paxdiablo 2009-01-28 06:39:06

@Pax: It looks like you have an answer already, but I was working on an image, so I'll post it anyway, for the sake of other readers: http://stackoverflow.com/questions/486473/how-would-you-handle-a-special-case-in-this-digital-logic-system#486723

e.James 2009-01-28 07:05:41

@Matt J: You're right about a synthesis tool being the way to go. I wanted the diagram to describe the inherent algorithm in a way that humans could understand so that the programmer would know how to write the logic description for the synthesizer :)

e.James 2009-01-28 07:08:50

Answer 2

A:

e.James 2009-01-28 07:04:45

Wouldn't it be better to arrange them in a tree?

finnw 2009-07-13 14:36:27

@finnw: Yes. A tree arrangement is optimal (and is probably what the synthesis tool will produce). I was just using the series setup to make the logic easier to read. :)

e.James 2009-07-13 16:00:12

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How would you handle a special case in this digital logic system?

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