Software performance (MCPS and Power consumed) in a Embedded system

Question

Assume an embedded environment which has either a DSP core(any other processor core).

If i have a code for some application/functionality which is optimized to be one of the best from point of view of Cycles consumed(MCPS) , will it also be a code, best from the point of view of Power consumed by that code in a real hardware system?

Can a code optimized for least MCPS be guaranteed to have least power consumption as well?

I know there are many aspects to be considered here like the architecture of the underlying processor and the hardware system(memory, bus, etc..).

Answer 1

Very difficult to tell without putting a sensitive ammeter between your board and power supply and logging the current drawn. My approach is to test assumptions for various real world scenarios rather than go with the supporting documentation.

Answer 2

No, lowest cycle count will not guarantee lowest power consumption.

It's a good indication, but you didn't take into account that memory bus activity consumes quite a lot of power as well.

Your code may for example have a higher cycle count but lower power consumption if you move often needed data into internal memory (on chip ram). That won't increase the cycle-count of your algorithms but moving the data in- and out the internal memory increases cycle-count.

If your system has a cache as well as internal memory, optimize for best cache utilization as well.

Answer 3

This isn't a direct answer, but I thought this paper (from this answer) was interesting: Real-Time Task Scheduling for Energy-Aware Embedded Systems.

As I understand it, it trying to run each task under the processor's low power state, unless it can't meet the deadline without high power. So in a scheme like that, more time efficient code (less cycles) should allow the processor to spend more time throttled back.