make

Make file echo displaying "$PATH" string.

I am trying to force make file to display next string: "Please execute next commands: setenv PATH /usr/local/greenhills/mips5/linux86:$PATH" The problem is with "$PATH". Command @echo "setenv PATH /usr/local/greenhills/mips5/linux86:$PATH" cause a result "setenv PATH /usr/local/greenhills/mips5/linux86:ATH" any combinations of e...

Setting basedirlist in setup.cfg and PREFIX in make to point to virtualenv

In SO question 3692928, I showed how I compiled and installed matplotlib in a virtualenv. One thing I did was suboptimal though—I manually set the basedirlist in setup.cfg and PREFIX in make.osx. setup.cfg [directories] basedirlist = /Users/matthew/.virtualenvs/matplotlib-test make.osx PREFIX=/Users/matthew/.virtualenvs/matplotlib-t...

Why does this makefile execute a target on 'make clean'

This is my current makefile. CXX = g++ CXXFLAGS = -Wall -O3 LDFLAGS = TARGET = testcpp SRCS = main.cpp object.cpp foo.cpp OBJS = $(SRCS:.cpp=.o) DEPS = $(SRCS:.cpp=.d) .PHONY: clean all all: $(TARGET) $(TARGET): $(OBJS) $(CXX) $(CXXFLAGS) $(LDFLAGS) $(OBJS) -o $(TARGET) .cpp.o: $(CXX) $(CXXFLAGS) -c $< -o $@ %...

Using a C extern function inside a C++ file: Linking issues with Makefile

Hello, I have an issue. I have defined in C file, read-line.c, a function print, like this: void history_print(void) { /* some stuff */ } In a C++ file, command.cc, I have the following: extern "C" void history_print(void); and then I simply call history_print(). #Use GNU compiler cc = gcc -g CC = g++ -g all: shell tty-r...

String comparison inside makefile

In a makefile, I'd like to define a variable specifying whether the current redhat-release is greater than 5.3. (This variable will be passed to gcc as a #define) So far I've come up with: # Find out which version of Red-Hat we're running RH_VER_NUM = $(shell /bin/grep -o [0-9].[0-9] /etc/redhat-release) RH_GT_5_3 = $RH_VER_NUM > '5.3'...

makefile pattern rules without recipes

I'm observing an interesting behavior of make and I wonder if there is a reasonable explanation to it besides a bug in gmake. Let's say we have the following in makefile: %-animal: echo "$* is an animal" %-fox: %-fox-animal %-wolf: %-wolf-animal The difference between the last two targets is that "%-wolf" does not have any ...

Translate makefile to produce static libxxx.a instead of dynamic libxxx.dylib

I am compiling a library (http://www.antisphere.com/Wiki/tools:anttweakbar) but issuing "make" with its included makefile on my mac produces a dynamic library (.dylib). I would much rather have a static library so that I can deploy it with my app. Is it easy/possible to translate the flags in the makefile to produce a static library? It...

How can I check with which options was program compiled?

Hi, I would like to know options which where passed to program before make, which is currently installed on my Ubuntu (from deb). I would like to compile it manualy with the same options (+ some extra). ...

multi-wildcard pattern rules of GNU Make

I want to write something like regex: SRC:="a.dat.1 a.dat.2" $(SRC): %.dat.%: (\\1).rlt.(\\2) dat2rlt $^ $@ so that a.dat.1 and a.dat.2 will give a.rlt.1 and a.rlt.2. In GNU Make info page, it says "the % can be used only once". Is there some trick to achieve this in GNU Make? ...

Easy makefiles for gcc/g++

My projects almst always consist of: 1- Pairs of Foo.h and Foo.cpp 2- Some extra headers util.h etc. What is the simplest way to write a makefile that a-runs $CC -c foo.cpp for each .cpp file, keeping a dependency to its coresponding .h file b- provides some way that I can manually add extra dependencies c-includes a linking s...

Why can't I build Perl modules that load Socket.so on Solaris 10?

I am trying to build Convert::ASN1 module but I get an error in the process. I am using Perl 5.12.0 on Solaris 10. perl Makefile.PL runs without trouble, same for make, but 'make test' throws this error: MOST CRUCIAL PART OF IT IMO: t/00prim.t ....... Can't load '/usr/local/lib/perl5/5.12.0/sun4-solari +s/auto/Socket /Socket.so' for mo...

Understanding Make's implicit rules

If I erase the gcc lines from this file shouldn't it take compilation as the implicit rule? Why isn't it allowing me to run the program ./calc with that makefile configuration? Makefile: all: calc clean: rm -rf calc arit.o calc.o calc: calc.o arit.o #gcc -o calc calc.o arit.o calc.o: calc.c arit.h #gcc -c calc.c a...

Help with Make error

When I run make I get an error: root@vagrantup:~/npm-1285112852/scripts# ./install.sh % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 100 568k 100 568k 0 0 267k 0 0:00:02 0:00:02 --:--:-- 466k node cli.js ca...

Exploding recursive make with libltdl

In my Makefile.am, I have SUBDIRS = libltdl . This is because I want to be able to use the version of libltdl included with my package (i.e. ./configure --with-included-ltdl). However, I occasionally run into the problem where make invokes itself recursively forever. Unfortunately I'm not sure exactly what conditions cause this to occ...

Makefile issue: smart way to scan directory tree for .c files

I am doing a project which is growingprety fast and keeping the object files up date is no option. The problem beyon wildcard command lies somewhere between "I do not want recursive makefiles" and "I do not want it to list by hand". The objects are supposed to go into a seperate diretory, which works allready. Note: I am not that used to...

How to add custom targets in a qmake generated Makefile?

Hi Today when I play with Qt I use qmake to generate the Makefile, and that works quite well. However sometimes I want to add more stuff to the generated Makefile, without having to edit the generated Makefile. Let's say that we beside the source code have a Doxygen directory, and there I need to run some doxygen commands to gener...

makefile for java

Hi, i don't understand what i did wrong with my makefile : JAVA_SRCS:=$(wildcard tasks/src/*.java) JAVA_CLASSES=$(subst /src/,/build/,$(JAVA_SRCS:.java=.class)) JFLAGS=-cp jar/octobot.jar -d tasks/build JC=javac .SUFFIXES: .java .class .java.class: $(JC) $(JFLAGS) $*.java default: build build: $(JAVA_CLASSES) clean: $(RM) tasks/...

Why use make over a shell script?

Make seems to me simply a shell script with slightly easier handling of command line arguments. Why is it standard to run make instead of ./make.sh ...

sed in makefile, usage

hi, I am in the process of learning makefile creation. Current target is to scan the $(SOURCEDIR) for .c files and create (according to that lise of .c file paths in the format of /path/file.c) a nice $(VPATH) so I do not need to use recursive makefiles (aka pain in the a..). Atm I am stuck with this, where $(SOURCETREE) will be empty ...

How do I get make to figure out the correct dependencies to link in the correct downstream object files?

I'm going to use a small example for reference. Consider a project with: inner_definitions.o : inner_definitions.cpp inner_definitions.h gcc $^ -o $@ inner_class_1.o : inner_class_1.cpp inner_class_1.h inner_definitions.h gcc $^ -o $@ inner_class_2.o : inner_class_2.cpp inner_class_2.h inner_definitions.h gcc $^ -o $@ ...