makefile

Defining variables for use in both Makefiles and Shell scripts

I'd like to distribute a set of build variables (which someone should append to their LDFLAGS), in a form that can both be included in a Makefile and in a shell script. What I have now is a file buildflags.conf: LDFLAGS_EXTRA="-static -foo -bar" I want my users to be able to, when they're using makefiles: include buildflags.conf LDF...

Makefile on terminal

Hi, I have seen a "basic Makefile tutorial" today, but I still don't understand a few things: What does the '&' character do in the line: "emacs Makefile &" ? After I have opened the emacs editor and created the Makefile file, how do I use it in order to compile my "source_code.c" file?? Thanks in advance, Sagiftw ...

Generating IDL entities using automake/Makefile.am

For those unfamiliar with IDL (interface description language), it abstracts data description for use across platforms (java, c, c++, etc). My project has dependencies Foo.c, Foo.h, FooHelper.c, and FooHelper.h which are generated from Foo.idl. How do I run an arbitrary command when Foo.idl changes, but still include Foo.c, FooHelper.c, ...

string comparation in Makefile

how to express this logic in Makefile? if $(XORG_VERSION) > "7.7" <do some thing> fi Conditional Parts of Makefiles only provides ifeq or ifneq. ...

Makefile.PL: Installing multiple scripts and binaries

Given a Makefile.PL, how can I install two binaries and two scripts in four different locations? To be more precise, the directory structure is as follows: lib/my_package/main.pl bin/daemon/daemon.pl (*) bin/plugin/plugin.pl (*) scripts/conf/conf.sh (*) scripts/init/initd.sh (*) Makefile.PL The files marked with (*) should be instal...

Performing greater-than less-than calculations in a Makefile

Hi, I'm trying to do this in a Makefile: value = 2.0 if ${greaterthan ${value}, 1.50} -> execute a rule elseif ${lessthan ${value}, 0.50} -> execute a rule endif Seems like quite a common thing to want to do, what's the best way of doing this? Thanks, Dan ...

What does it mean to 'touch' a target in make?

For example, from the mingw32-make.exe --help option: -t, --touch Touch targets instead of remaking them. ...

Cutting a string after occurrence of sub-string in a Makefile

I am writing a Makefile which needs to figure out the directory of an installed program, which can be found in PATH; or that is to say, is assumed to be in PATH. For example: if the binary is /opt/Xilinx/12.1/ISE_DS/ISE/bin/lin64/xst, then the path I am looking for is /opt/Xilinx/12.1/ISE_DS/ISE. The program could also be found as /home...

Cross compiling a kernel module

I'm trying to cross compile a helloworld kernel (2.6.x) module for ARM architecture on my intel x86 host. The codesourcery tool chain for ARM is located at: /home/ravi/workspace/hawk/arm-2009q3 The kernel source is located at :/home/ravi/workspace/hawk/linux-omapl1 My Makefile: ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabi obj-m := H...

What do @, - and + do as prefixes to recipe lines in Make?

In the GNU Makefile manual, it mentions these prefixes. If .ONESHELL is provided, then only the first line of the recipe will be checked for the special prefix characters (‘@’, ‘-’, and ‘+’). What do these prefixes do, and where are they mentioned? ...

Suppress make rule error output

I have an rule that creates a directory bin: -mkdir $@ However after the first time the directory has been generated, I receive this output: mkdir bin mkdir: cannot create directory `bin': File exists make: [bin] Error 1 (ignored) Is there some way I can only run the rule if the directory doesn't exist, or suppress the output w...

Makefile and QTCreator

I am new to programming under linux and not familiar with makefiles since MSVC-Express hides such things very well. But now i wanted to play with some code I found, but it won't compile in qtcreator. But with the makefile in the package i can successfully compile and use it. So all dependencies (libraries and headerfiles) must be correct...

Are makefiles Turing complete?

Lately at work, I've been doing some translation from Makefiles to an alternative build system. I've seen some pretty hairy Make code in some places using functional map, filter, and foreach constructs. This surprised me since I think build scripts ought to be as declarative as possible. Anyway, this got me thinking: is the Makefile lan...

including static library to ./configure

how do i include two static library while executing the command ./configure. Ex: ./configure --prefix=/usr \ LDFLAGS="-L/home/lancy/dictionary/src/WordNet-3.0/lib -lWN" here only one static library is include. how do i add such another static library to LDFLAGS in the same command. ...

Eclipse CDT error: "make: *** [src/test2.o] Error 127"

On Windows XP I've installed Eclipse CDT. I've installed cygwin including make, gcc, g++, and gdb. I've added C:\cygwin\bin to the windows path variable. When I create the default HelloWorld project in Eclipse and try to build, I get the following text in the console: make all make: echo: Command not found make: * [src/...

Compile other external libraries (without CMakeLists.txt) with CMake

short -- Is it possible to build a external binary/library out of a project with CMake, when the binary/library only has a makefile given? So you have your own project, a bunch of CMakeLists.txt in your src-tree and this external library with its source-files. Your sources depend on this library and some binaries/libraries want to link ...

Make file: compiling all .cpp files to .o files

I'm trying to create a make file which will compile all the .cpp files in the test directory to .o files in the obj directory. Below is an abridged version of what I am doing. The problem is that the calls made to compile to the .o files have the proper .o name, but they all are compiling the same .cpp file. gcc -c -o obj/foo.o test/f...

Subdirectories and Makefiles

I think this is a question that has been asked many times but I cannot find the right way to do it. I have the following structure: project/ project/Makefile project/code project/code/*.cc project/code/Makefile When I am in the directory 'project/code' and call "make project_code" my code is compiling correctly. I would like to do t...

using openmp with a makefile and g++

I am building a large project with a makefile that was originally built with icpc, and now I need to get it running with g++. When it compiles the file that uses openmp, it uses the -c flag, and doesn't use any libraries, so it ends up being serial instead of openmp. All of the examples I am seeing aren't using this -c flag. Is there s...

How to read file from Makefile?

I am using GNU Make to build a multiple-directory project. My question is how can I use single makefile to build multiple devices? e.g. My application has to run on various X,Y,Z mobile devices each having different properties like screensize, keyboard type, platform version etc. I have to pass make -f <makefilename> <targetname>. Here...