Recently as I am working with the hardware design group developing an ASIC. And I am drawing a lot of timing diagrams for which I am using Microsoft EXCEL to draw them, as it is easy to import to word document. But, things are getting more and more difficult with EXCEL. My question? How do you guys draw timing diagrams? Is there any eas...
Is there a TAP (Test Anything Protocol) implementation for Verilog? It would be nice because then I could use prove to check my results automatically. Update: 10/9/09: It was asked why not use assertions. Partly TAP gives me some good reporting such as number of files and number of tests. It also can be used with smolder for reportin...
In (regular) software I have worked at companies where the gcc option -Wall is used to show all warnings. Then they need to be dealt with. With non-trivial FPGA/ASIC design in Verilog or VHDL there are often many many warnings. Should I worry about all of them? Do you have any specific techniques to suggest? My flow is mainly for FP...