digital-logic

How would you handle a special case in this digital logic system?

I posted this digital logic diagram as an answer to another stackoverflow question. It describes a logic system which will be coded in Verilog or VHDL and eventually implemented in an FPGA. The numbered boxes in the diagram represent bits in a field. Each field has K bits, and the bits for current and mask will be provided by a comput...

How CPUs implement Instructions like MUL/MULT?

In different assembly languages MUL (x86)/MULT (mips) refer to multiplication. It is a black box for the programmer. I am interested in how actually a CPU accomplishes a multiplication regardless of the architecture. Lets say I have two 16-bit values in my registers and I am the cpu, so I have to implement MUL using the other bit-fiddlin...

Programmable Logic Devices

Dear all, I have a confusion in understanding the structure of PAL device. My first question is that if we buy a PAL device , then how can we know that how many min terms are added by each OR gate in the OR array? In other words I am asking, is there any standard by which we can know the number inputs each OR gate has in the OR arr...

Digital Circuit understanding

In my quest for getting some basics down before I start going into programming I am looking for essential knowledge about how the computer works down at the core level. I have a theory that actually understanding what for instance a stackoverflow let alone a stack is, instead of my sporadic knowledge about computer systems, will help m...

How to define clock input in Xilinx

Hey, I have almost no experience with Xilinx. I have a group project for a Digital Logic course that is due soon, where my partner, who was supposed to take care of the Xilinx simulations decided to bail on me. So here I am trying to figure it out last minute. I have designed a synchronous counter using a few JK Flip Flops and I need to...

Help with odd number dividers (digital)

I am reading this: http://www.onsemi.com/pub_link/Collateral/AND8001-D.PDF On page three, the logic equations is given for the divide-by 9 DFF circuit. How do I obtain the equations through k-maps? I know to use k-maps, but I dont know what and how they are filling the k-maps with to obtain: Ad = A*B* Bd = A*B + AB* Cd = ABC* + CB*...

Linear feedback shift register?

Lately I bumped repeatedly into the concept of LFSR, that I find quite interesting because of its links with different fields and also fascinating in itself. It took me some effort to understand, the final help was this really good page, much better than the (at first) cryptic wikipedia entry. So I wanted to write some small code for a p...