fpga

Reset an Altera M9K's content to 0 (power-up value)

Good day, I am working on a Stratix III FPGA which contains M9K block memories, the contents of which are conveniently initialised to zero on power-on. This suits my application very well. Is there a way to reset the contents back to zero without power-cycling/reflashing/etc the FPGA? There seems to be no such option in the megawizard ...

Looking for library declaration of IP Module

Hi, I want to use the Xilinx hardware module of the ICAP controller in my own design. This module uses the following library: library hwicap_v5_00_a; use hwicap_v5_00_a.all; I was looking in the directories as well as subdirectories of Xilinx\12.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores but I could not find the package declarati...

Logical Operator problem VHDL

Hi, I have a very simple operator problem in VHDL. I try to compare some inputs with logical operators but get an error message... entity test is port ( paddr : in std_logic_vector(15 downto 0); psel : in std_logic; penable : in std_logic; pwrite : in std_logic ); en...

How do I implement a synthesizable DPLL in Verilog?

Is there any straight forward way to implement an all digital phase lock in synthesizable Verilog? Everything (including the VCO) should be synthesized. The signals I'm looking to lock to are ~0.1-1% of the system clock frequency. I am using one that I've reconstructed from 1980's IEEE papers, but it doesn't behave as well as advertised....

Problem adding std_logic_vectors

Hi, I wanna have a simple module that adds two std_logic_vectors. However, when using the code below with the + operator it does not sythesis. library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity add_module is port( pr_in1 : in std_logic_vector(31 downto 0); pr_in2 : in std_logic_vector(31 d...