fpga

Verilog code simulates but does not run as predicted on FPGA

I did a behavioral simulation of my code, and it works perfectly. The results are as predicted. When I synthesize my code and upload it to a spartan 3e FPGA and try to analyze using chipscope, the results are not even close to what I would have expected. What have I done incorrectly? http://pastebin.com/XWMekL7r ...

Development process for an embedded project with significant hardware changes

I have a good idea about Agile development process but I have no ieda how to map that to a embedded project with significant hardware changes. I will describe below what we are currently doing (Ad-hoc way, no defined process yet). The changes are divided into three categories and different processes are used for each of them: compl...

Should you remove all warnings in your Verilog or VHDL design? Why or why not?

In (regular) software I have worked at companies where the gcc option -Wall is used to show all warnings. Then they need to be dealt with. With non-trivial FPGA/ASIC design in Verilog or VHDL there are often many many warnings. Should I worry about all of them? Do you have any specific techniques to suggest? My flow is mainly for FP...

FPGA Filter Project

Do you guys have any good ideas on FPGA projects involving a filter? I want to do something interesting... not sure what. Thanks ahead of time. ...

Looking for a micro programmable FPGA + machine

Hi! I'm looking for a FPGA + machine. It should be entry level pricing (e.g no more than $200). EDIT: I want to make an ASM chart and program the FPGA to act like I specified in the chart ...

Python socket for receiving UDP packages from an FPGA

Hello everybody, I am trying to read the UDP packages in python, which were sent from an FPGA. I see the packages in wireshark, and they look allright. Python, however does not receive anything when I use this simple script: import socket import sys HOST, PORT = "192.168.1.1", 21844 sock = socket.socket(socket.AF_INET, socket.SOCK_DGRA...

Algorithms FPGAs dominate CPUs on

Hi! For most of my life, I've programmed CPUs; and although for most algorithms, the big-Oh running time remains the same on CPUs / FPGAs, the constants are quite different (for example, lots of CPU power is wasted shuffling data around; whereas for FPGAs it's often compute bound). I would like to learn more about this -- anyone know o...

JIT-ing on FPGAs ?

Many VMS, JVM/LLVM/... have JITs -- as the code is being interpreted, x86 instructions are created on the fly and executed. If there something similar to this for FPGAS? Is there someway where as an FPGA is running, I reconfigure it? [If so, please provide project / paper links. If not, what is the technology bottleneck that prevents th...

FPGA Place & Route

For programming FPGAS, is it possible to write my own place & route routines? [The point is not that mine would be better; the point is whether I have the freedom to do so] -- or does the place & route stage output into undocumented bitfiles, essengially forcing me to use proprietary tools? Thanks! ...

Configuration Management for FPGA Designs

Which configuration management tool is the best for FPGA designs, specifically Xilinx FPGA's programmed with VHDL and C for the embedded (microblaze) software? ...

Signals and Variables in VHDL (order) - Problem

I have a signal and this signal is a bitvector (Z). The length of the bitvector depends on an input n, it is not fixed. In order to find the length, I have to do some computations. Can I define a signal after defining the variables ? It is giving me errors when I do that. It is working fine If I keep the signal before the variables (that...

Generating a pure sine wave as output form FPGA using VHDL code

We know that the output of an FPGA is digital but can we genrate a pure analog sine wave using a vhdl code. also can I specify the frequency of the sine wav. ...

Ultra-fast bitmap rendering using WPF, best solution ?

Hello there, I'm getting from our hardware device (FPGA) roughly 20 frames per second (500x500 px) and I would like to render them as fast as possible. We basically get a frame buffer every 50 msec and if my rendering is too slow - well... I'm skipping frames. My problem is to render from a C++/CLI driver to a WPF-based application. I ...

Import Code from FPGA Board (Spartan 3E)

Is there any way to import code from an already programmed FPGA board, in this case, it is a Spartan 3E board. That is to say, verilog code has already been uploaded to it, so I would like a way to receive the code back in the computer since I have lost the copy. I uploaded the code with Xilinx ISE, but am not sure if it is possible to g...

Splitting an ELF executable into two files in an embedded system

Hi, I use Xilinx Microblaze CPU core in Virtex4 FPGA. I would like to add a new code part to my current code, but then my code will exceed the size of the flash it is burnt to. Therefore I want to burn the added code to another flash. My code is copied to RAM by a boot loader, which then jumps to RAM and starts regular execution. I int...

Starting FPGA Programming

I want to start FPGA programming. I don't have any knowledge at all about how FPGAs work and such. I would like to get a development board, not too expensive, but it should have at least 40 I/O pins. Anything up to $300 is OK. I decided that I want to program in Verilog. I am not sure about the following: How will my compiled 'program...

Sending UDP packets via Java

Hi all, I'm trying to send UDP packets from my PC to an FPGA via my laptop's ethernet cable. I've been using Java's DatagramPacket and DatagramSocket to send the UDP packets. However, these packets will only send over my laptop's wireless interface. How can I specify that the packets should go through my ethernet interface? Thank you. ...

[VHDL] how much for Sound (ADC) reading in 24khz?

Hi there, how much "sound inputs" of high fidelify (128K 44kH) may be made via ordinary FPGA (Xilinx Spartan 3, what-so-ever) without using external ADC converters (only voltage-balanced input optically taken from audio jack)? Here, http://stackoverflow.com/questions/3165266/generating-a-pure-sine-wave-as-output-form-fpga-using-vhdl-cod...

Simple State Machine Problem

Hi all, I have a very simple FSM which should drive some output signals of an external RAM. The problem that I have comes with handling the data bus which can be input as well as output... I am not too sure how I can handle best this case in my FSM. The problem comes from the following line: v.sram_data <= io_sram_data; Obviously...

State to std_logic

Hi all, I have defined my state as follows: type state_type is (s0, s1, s2, s3); signal state : state_type; Now I would like to use this state information to form another signal signal data : std_logic_vector(3 downto 0); signal data_plus_state : std_logic_vector(5 downto 0); .... data_plus_state <= data & state; Does anyone kn...